Re: Wait State 00050064

"Robert Schreiber [email protected] [H390-MVS]" <[email protected]>
Newsgroups gmane.comp.emulators.hercules390.mvs
Message-ID <[email protected]>
Here is a scenario that causes

IEA304W SYSTEM WAIT STATE - CODE 00050064
immediately after
IEA101A SPECIFY SYSTEM PARAMETERS FOR RELEASE 03.8 .VS2

In my Hercules 4 configuration I had LPARNUM 01 instead of LPARNUM BASIC.

Why did this matter?

I did a lot of tracing, etc and found that NIP (Nucleus Initialization
Program) was
getting an 80A abend by asking for a huge amount of memory. What was going
on is that
bytes 6-7 in the result of an STIDP instruction was being used to calculate
the amount of
memory get. I have no idea what MVS is try to accomplish here--this has to
be an MVS bug.

Referring to SA22-7201-08, Pages 10-90/91:

"The format bit (F) in bit position 48 specifies the format of the first two
digits of the
CPU identification number."

"When the format bit is zero, the contents of the CPU-identification-number
field, in
conjunction with the machine-type number, permit unique identification of
the CPU."

"When the format bit is one, the CPU-identification number identifies the
system
configuration as opposed to an individual CPU within the configuration, and
it identifies
the logical partition in which the program is being executed."

Programming Note 6: "The format bit is always stored as a zero is the basic
mode."

I had an LPARNUM 01 in my configuration and therefore STIDP was returning
F=1 (which is
correct).

However, for some reason beyond me, MVS 3.8J is using the half-word at bytes
6-7 (0x8000)
in an AH instruction to compute the amount of memory for the GETMAIN.

By setting LPARNUM BASIC I was able to set F=0 and the system came up OK.

Here's my proof...

The MVS code in question:

R:000000000000B426  B202C47C     STIDP 1148(12)               store_cpu_id
R:000000000000B42A  41800148     LA    8,328(0,0)             load_address
R:000000000000B42E  4A80C482     AH    8,1154(0,12)           add_halfword
R:000000000000B432  5980C438     C     8,1080(0,12)           compare
R:000000000000B436  4720C02C     BC    2,44(0,12)            
branch_on_condition
R:000000000000B43A  410000F5     LA    0,245(0,0)             load_address
R:000000000000B43E  89000018     SLL   0,24(0)               
shift_left_single_logical
R:000000000000B442  1608         OR    0,8                    or_register
R:000000000000B444  4510C094     BAL   1,148(0,12)           
branch_and_link
R:000000000000B448  0A0A         SVC   10                    
supervisor_call

Here's a trace leading up to the 80A abend...

PSW=070C00000000B426 INST=B202C47C     STIDP 1148(12)              
store_cpu_id
R:0000B830  00123456 01688000                    ........
                         ^
                         +-- Note F=1 becauase LOADPARM is not "BASIC"

GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=00FFE1F0 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390


Apparently we want 328 bytes + value of STIDP+6(2) which
makes no sense to me. STIDP+6 is always 8000 or 0000.

PSW=070C00000000B42A INST=41800148     LA    8,328(0,0)            
load_address
V:00000148:K:06=00000000 00000000 00000000 00000000  ................
GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=00FFE1F0 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

I have no idea what MVS is trying to do here...
PSW=070C00000000B42E INST=4A80C482     AH    8,1154(0,12)          
add_halfword
V:0000B836:K:06=8000 47F0F01E 18C9C7C6 D7C5E7C9 E340 ...00..IGFPEXIT
                ^
                +--  F=1,  Makes this add =328-32768 which is FFFF8148

GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=00000148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

I have no idea what this is testing for...
PSW=070C10000000B432 INST=5980C438     C     8,1080(0,12)           compare
V:0000B7EC:K:06=00000FFF FFFFFFFC 00000100 00000080  ................
GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

PSW=070C10000000B436 INST=4720C02C     BC    2,44(0,12)            
branch_on_condition
V:0000B3E0:K:06=41F00004 58E0D00C 980CD014 07FE5910  .0...\}.q.}.....
GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

Subpool 245...
PSW=070C10000000B43A INST=410000F5     LA    0,245(0,0)            
load_address
V:000000F5:K:06=000000 00000000 00000000 00000000 00 ................
GR00=00000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

PSW=070C10000000B43E INST=89000018     SLL   0,24(0)               
shift_left_single_logical
V:00000018:K:06=00000000 00000000 070C2000 00D99C2A  .............R..
GR00=000000F5 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

Or-in the length, buts since is negative we blow away
the subpool 245 that we had in the left byte
PSW=070C10000000B442 INST=1608         OR    0,8                   
or_register
GR00=F5000000 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

Indicate REGMAIN if I recall correctly...
PSW=070C10000000B444 INST=4510C094     BAL   1,148(0,12)           
branch_and_link
V:0000B448:K:06=0A0A1851 501020A0 B1410000 504020A4  ....&.......& .u
GR00=FFFF8148 GR01=00000000 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

R0 is messed up with wrong subpool and bad length...
PSW=070C10000000B448 INST=0A0A         SVC   10                    
supervisor_call
GR00=FFFF8148 GR01=9000B448 GR02=00FFE1F0 GR03=00018A40
GR04=80000001 GR05=0008B518 GR06=00009718 GR07=00000005
GR08=FFFF8148 GR09=00FFEEA8 GR10=00000000 GR11=00000000
GR12=6000B3B4 GR13=001E7F44 GR14=601E7E00 GR15=0000B390

Processor CP00: disabled wait state 00020000 80050064




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