RE: Re: Wait State 00050064

> -----Original Message-----
> From: [email protected] <[email protected]>
> Sent: 20 September 2019 16:34
> To: [email protected]
> Subject: [H390-MVS] Re: Wait State 00050064
> 
> Here is a scenario that causes
> 
> IEA304W SYSTEM WAIT STATE - CODE 00050064 immediately after IEA101A
> SPECIFY SYSTEM PARAMETERS FOR RELEASE 03.8 .VS2
> 
> In my Hercules 4 configuration I had LPARNUM 01 instead of LPARNUM BASIC.
> 
> Why did this matter?
> 
> I did a lot of tracing, etc and found that NIP (Nucleus Initialization
> Program) was
> getting an 80A abend by asking for a huge amount of memory. What was going
> on is that bytes 6-7 in the result of an STIDP instruction was being used
to
> calculate the amount of memory get. I have no idea what MVS is try to
> accomplish here--this has to be an MVS bug.
> 
> Referring to SA22-7201-08, Pages 10-90/91:
> 
> "The format bit (F) in bit position 48 specifies the format of the first
two digits
> of the CPU identification number."
> 
> "When the format bit is zero, the contents of the
CPU-identification-number
> field, in conjunction with the machine-type number, permit unique
> identification of the CPU."
> 
> "When the format bit is one, the CPU-identification number identifies the
> system configuration as opposed to an individual CPU within the
configuration,
> and it identifies the logical partition in which the program is being
executed."
> 
> Programming Note 6: "The format bit is always stored as a zero is the
basic
> mode."
> 
> I had an LPARNUM 01 in my configuration and therefore STIDP was returning
> F=1 (which is
> correct).
> 

I am not so sure about that. It goes on to say that for the z800 and z900
bit 48 is always zero....
.... but there again I don't think a Z800 or Z900 can provide S/370 LPARS...

The function characteristics manual for the ES9000 also says that the final
four digits of the result is always zero....

http://chiclassiccomp.org/docs/content/computing/IBM/Mainframe/Hardware/Syst
em/GA22-7138-02_ESystem9000-330-720FunctionalCharConfig_Sep91.pdf

.... so whilst the architecture manual says in LAPR mode bit 48  should be
"1" in practice it looks like for many machines its "0".

I can't check for the ES9221 as I can't find a Functional Specification for
that.

Also in a 370 mode LPAR the STDIP instruction shouldn't behave live a real
S/370...

Dave