[RFC PATCH v2 0/2] hw/i2c, hw/misc: emulated Xilinx AXI-IIC controller + PCIe FPGA carrier

Hi all,

This is a follow-up to the single-patch RFC I sent last week ("[RFC
PATCH 1/1] hw/misc: add xiic-fpga-i2c, an emulated PCIe FPGA I2C
controller"). Based on the split suggested there between a
standardized controller and its carrier, this v2 breaks the device in
two:

  1/2 - hw/i2c: a generic model of the AMD/Xilinx AXI IIC controller
        (LogiCORE IP, PG090) as a SysBus device, independent of any
        particular carrier.
  2/2 - hw/misc: a PCIe function, gated behind TEST_DEVICES, that
        embeds N of the above controllers behind one BAR0 window and
        aggregates their interrupts onto a single MSI vector (with a
        legacy INTx fallback). This models a specific FPGA carrier
        rather than a standardized board, hence hw/misc + TEST_DEVICES
        rather than hw/i2c proper.

Together they let the Linux i2c-xiic driver, and any I2C slave behind
it, be exercised under QEMU without real hardware.

Changes since v1:
  - Split the single device into a generic hw/i2c controller model and
    a separate hw/misc PCIe carrier that instantiates it.
  - Added a register-level spec for the controller
    (docs/specs/xlnx-axi-iic.rst).
  - Added a qtest (tests/qtest/xiic-fpga-i2c-test.c) that drives a
    transfer through BAR0 to a tmp105 slave and checks register,
    transfer and NACK behavior.
  - Reworded comments/commit messages to describe the hardware in
    generic terms rather than referencing a specific downstream
    project.

Open questions (carried over / updated from v1):

  1. Is hw/misc + TEST_DEVICES the right home for the carrier, given
     the controller itself is now a standalone hw/i2c device? I split
     it this way since the carrier's register aggregation is specific
     to one FPGA design rather than a standardized board.

  2. The AXI-IIC register decode is deliberately partial: it
     implements the subset the Linux i2c-xiic driver actually touches
     in dynamic mode. I can flesh out static/manual mode if that is
     preferred for a general-purpose model.

This series is based on current master. Happy to add more qtest
coverage or documentation if there's interest in merging either half.

Thanks

Nodoka Shibasaki (2):
  hw/i2c: add xlnx-axi-iic, a Xilinx AXI IIC controller
  hw/misc: add xiic-fpga-i2c, a PCIe FPGA embedding xlnx-axi-iic cores

 MAINTAINERS                                |  12 +
 configs/devices/x86_64-softmmu/default.mak |   5 +
 docs/specs/index.rst                       |   1 +
 docs/specs/xlnx-axi-iic.rst                |  62 +++++
 hw/i2c/Kconfig                             |   4 +
 hw/i2c/meson.build                         |   1 +
 hw/i2c/xlnx-axi-iic.c                      | 284 +++++++++++++++++++++
 hw/misc/Kconfig                            |   6 +
 hw/misc/meson.build                        |   1 +
 hw/misc/xiic_fpga_i2c.c                    | 261 +++++++++++++++++++
 include/hw/i2c/xlnx-axi-iic.h              |  69 +++++
 tests/qtest/meson.build                    |   2 +
 tests/qtest/xiic-fpga-i2c-test.c           | 159 ++++++++++++
 13 files changed, 867 insertions(+)
 create mode 100644 docs/specs/xlnx-axi-iic.rst
 create mode 100644 hw/i2c/xlnx-axi-iic.c
 create mode 100644 hw/misc/xiic_fpga_i2c.c
 create mode 100644 include/hw/i2c/xlnx-axi-iic.h
 create mode 100644 tests/qtest/xiic-fpga-i2c-test.c

-- 
2.50.1