[PATCH 1/2] tcg/mips64: Fix variable shift operand order

From: Quintin Kong <[email protected]>

TCGOutOpBinary passes (output, value, count), but MIPS variable shift
instructions encode (rd, rt, rs), where rt is the value and rs is the
count. tcg_out_opc_reg() takes its register fields in (rd, rs, rt)
order, so passing (a0, a1, a2) encodes the value as the count and the
count as the value.

Swap a1 and a2 at the four variable shift emitters. This covers the I32
and I64 forms of SHL, SHR, SAR, and ROTR.

Cc: [email protected]
Fixes: 03568c0d5395 ("tcg: Convert rotl, rotr to TCGOutOpBinary")
Fixes: b5aafbaa8346 ("tcg: Convert sar to TCGOutOpBinary")
Fixes: 27d21ee7c791 ("tcg: Convert shl to TCGOutOpBinary")
Fixes: edd6ba8a6bc8 ("tcg: Convert shr to TCGOutOpBinary")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4103
Signed-off-by: Quintin Kong <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
---
 tcg/mips/tcg-target.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 400eafbab4..29cf7fa0ab 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2049,7 +2049,7 @@ static void tgen_rotr(TCGContext *s, TCGType type,
                      TCGReg a0, TCGReg a1, TCGReg a2)
 {
     MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV;
-    tcg_out_opc_reg(s, insn, a0, a1, a2);
+    tcg_out_opc_reg(s, insn, a0, a2, a1);
 }
 
 static void tgen_rotri(TCGContext *s, TCGType type,
@@ -2073,7 +2073,7 @@ static void tgen_sar(TCGContext *s, TCGType type,
                      TCGReg a0, TCGReg a1, TCGReg a2)
 {
     MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV;
-    tcg_out_opc_reg(s, insn, a0, a1, a2);
+    tcg_out_opc_reg(s, insn, a0, a2, a1);
 }
 
 static void tgen_sari(TCGContext *s, TCGType type,
@@ -2096,7 +2096,7 @@ static void tgen_shl(TCGContext *s, TCGType type,
                      TCGReg a0, TCGReg a1, TCGReg a2)
 {
     MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV;
-    tcg_out_opc_reg(s, insn, a0, a1, a2);
+    tcg_out_opc_reg(s, insn, a0, a2, a1);
 }
 
 static void tgen_shli(TCGContext *s, TCGType type,
@@ -2119,7 +2119,7 @@ static void tgen_shr(TCGContext *s, TCGType type,
                      TCGReg a0, TCGReg a1, TCGReg a2)
 {
     MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV;
-    tcg_out_opc_reg(s, insn, a0, a1, a2);
+    tcg_out_opc_reg(s, insn, a0, a2, a1);
 }
 
 static void tgen_shri(TCGContext *s, TCGType type,
-- 
2.43.0