[PATCH 0/2] target/riscv: Fix seed CSR sign extension

The seed CSR value on RV64 was sign extended while converting to target_ulong.

The first patch makes SEED_OPST_* unsigned.
The second patch adds qtest to check that upper 32 bits are zero.

Tests ran:
- riscv-csr-test
- make check: 324 passed, 11 skipped
- RISC-V Zkr-00 architectural test

Ivan Efremov (2):
  target/riscv: Fix seed CSR sign extension
  tests/qtest: Add seed CSR zero extension test

 target/riscv/cpu_bits.h      | 10 +++++-----
 tests/qtest/riscv-csr-test.c | 26 ++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 5 deletions(-)

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2.43.0