Re: [PATCH v2 1/5] hw/ssi: Add Synopsys DesignWare SSI standard PIO controller

Hi
Chao Liu <[email protected]> 于2026年8月3日周一 10:10写道：

> Could you share a stable public link to the DesignWare SSI datasheet here?

Sorry, but I don't have a stable public link to share. Synopsys
doesn't publish the DesignWare SSI databook for public download; it's
gated behind myDesignWare registration.

As for the other Synopsys peripherals, I haven't seen any public links
to Synopsys IP documentation either - not for the existing QEMU models
(DWC2/DWC3 USB, DesignWare I2C, DesignWare PCIe host, etc.) or
anywhere else.

I actually referenced for this implementation:

- K230 TRM (Canaan official; includes the DWC SSI 1.01a register
descriptions): https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf

- Intel Arria 10 HPS TRM, Chapter 20 (Intel official; DW APB SSI
registers) https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/hard-processor-system-technical-reference.html

- Intel HPS Technical Reference Manual:
https://www.intel.com/content/www/us/en/docs/programmable/683222/22-4/hard-processor-system-technical-reference.html

- Linux kernel DW SPI driver,
  - DT binding:
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
  - Driver header (PSSI/HSSI CTRLR0 ):
https://github.com/torvalds/linux/blob/master/drivers/spi/spi-dw.h
  - Driver core
https://github.com/torvalds/linux/blob/master/drivers/spi/spi-dw-core.c