Re: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled

On 8/3/26 15:26, Duan, Zhenzhong wrote:
> Hi Clement,
> 
>> -----Original Message-----
>> From: Clément MATHIEU--DRIF <[email protected]>
>> Subject: [PATCH v1] intel_iommu: Expose SMPWC when SVM is enabled
>>
>> SVM in Linux requires SMPWC as of 780dfed68862. This is free in the
>> current implementation as it is already in line with the expected
>> behaviour.
> 
> Not an issue in this patch, what about 'C: Page-walk Coherency' ecap bit,
> I think we can enable it too? Maybe in another patch?
> 
>>
>> Signed-off-by: Clement Mathieu--Drif <[email protected]>
>> ---
>> hw/i386/intel_iommu.c          | 3 ++-
>> hw/i386/intel_iommu_internal.h | 1 +
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 8245452d89..9f21622a4f 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -5108,7 +5108,8 @@ static void vtd_init(IntelIOMMUState *s)
>>      }
>>
>>      if (s->svm) {
>> -        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
>> +        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
>> +                   VTD_ECAP_SMPWCS;
> 
> I think we need a check for passthrough device to expose SMPWCS, something like below pseudo code:

thumb up. yes.  It's strange guest reports SMPWCS while host does not.

> @@ -37,6 +37,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
>           return false;
>       }
> 
> +    if (VTD_ECAP_GET_SMPWCS(s->ecap) && !VTD_ECAP_GET_SMPWCS(vtd->cap_reg)) {
> +        error_setg(errp,
> +                   " Scalable-Mode Page-walk Coherency is unsupported by host IOMMU");
> +        return false;
> +    }
> +
>       if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) {
>           error_setg(errp,
>                      "First stage 1GB large page is unsupported by host IOMMU");
> 
>>      }
>>
>>      vtd_reset_caches(s);
>> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
>> index 924e91cb8a..df7a0efa6e 100644
>> --- a/hw/i386/intel_iommu_internal.h
>> +++ b/hw/i386/intel_iommu_internal.h
>> @@ -202,6 +202,7 @@
>> #define VTD_ECAP_SMTS               (1ULL << 43)
>> #define VTD_ECAP_SSTS               (1ULL << 46)
>> #define VTD_ECAP_FSTS               (1ULL << 47)
>> +#define VTD_ECAP_SMPWCS             (1ULL << 48)
>>
>> /* CAP_REG */
>> /* (offset >> 4) << 24 */
>> --
>> 2.54.0