Re: [PATCH] target/i386: fix incorrect decoding of EXTRQ_i

Ping. Just checking if this patch might have been missed, or if anyone
has time to take a look. Please let me know if any changes are needed!

On Thu, Jun 25, 2026 at 5:56 PM Simon Scherer <[email protected]> wrote:
>
> The decoding of the extrq instruction with an immediate operand (EXTRQ_i) is
> incorrect. Per the AMD manual the instruction encoding looks as follows:
>
> EXTRQ xmm1, imm8, imm8   66 0F 78 /0 ib ib
>
> The /0 indicates that the "Reg" field of the ModR/M byte must be equal
> to 0 and the XMM register operand is specified by the "R/M" field.
> However, qemu incorrectly uses the "Reg" field to extract the register operand.
>
> This patch instead extracts the XMM register operand from the "R/M"
> field.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3611
> Signed-off-by: Simon Scherer <[email protected]>
> ---
>  target/i386/tcg/decode-new.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
> index ac181308ca..acb300457c 100644
> --- a/target/i386/tcg/decode-new.c.inc
> +++ b/target/i386/tcg/decode-new.c.inc
> @@ -605,7 +605,7 @@ static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
>  {
>      static const X86OpEntry opcodes_0F78[4] = {
>          {},
> -        X86_OP_ENTRY3(EXTRQ_i,       V,x, None,None, I,w,  cpuid(SSE4A)), /* AMD extension */
> +        X86_OP_ENTRY3(EXTRQ_i,       U,x, None,None, I,w,  cpuid(SSE4A)), /* AMD extension */
>          {},
>          X86_OP_ENTRY3(INSERTQ_i,     V,x, U,x, I,w,        cpuid(SSE4A)), /* AMD extension */
>      };
> --
> 2.53.0
>