[PATCH v7 0/8] target/riscv: Support the true Zicclsm extension

From: Frank Chang <[email protected]>

Support the true Zicclsm extension so that we can trap misaligned accesses
when Zicclsm is disabled.

To enable/disable Zicclsm, simply set zicclsm=[true|false], e.g.:
  -cpu rv64,zicclsm=[true|false]

QEMU will raise a misaligned load/store exception when executing misaligned
load/store instructions if Zicclsm is disabled.

Changelog:
  v7:
    * Raise the misaligned exceptions for floating-point instructions
      (RVF, RVD, Zfh) when Zicclsm is disabled.
    * Add Zicclsm unit tests.
  v6:
    * Reorder and squash Zicclsm CPU property and RVA22U64 profile patches to
      make every single commit to pass `make check`.
  v5:
    * Add Zicclsm to RVA22U64 profile explicitly.
    * Rebase to the latest riscv-to-apply.next.
  v4:
    * Align ROM reset vector data at 8-byte aligned offsets.
  v3:
    * Enable Zicclsm for the compatible CPUs.
    * Rebase to the latest riscv-to-apply.next.
  v2:
    * Use (size_memop(size) | mo_endian_env(env)) to calculate MemOp.
    * Use (log2_esz << MO_ASHIFT) to calculate aligment MemOp for
      vector load/store whole register instructions.


Frank Chang (8):
  target/riscv: Add Zicclsm CPU option
  target/riscv: Enable Zicclsm for the compatible CPUs
  hw/riscv: sifive_u: Align ROM reset vector data
  target/riscv: Support raising misaligned exceptions for scalar
    loads/stores
  target/riscv: Support raising misaligned exceptions for floating-point
    loads/stores
  target/riscv: Support raising misaligned exceptions for vector
    loads/stores
  target/riscv: Expose Zicclsm as a CPU property and update RVA22U64
    profile
  tests/tcg/riscv64: Add test for Zicclsm

 hw/riscv/sifive_u.c                           |  11 +-
 target/riscv/cpu.c                            |  10 +-
 target/riscv/cpu_cfg_fields.h.inc             |   2 +
 target/riscv/tcg/insn_trans/trans_rvd.c.inc   |   6 +
 target/riscv/tcg/insn_trans/trans_rvf.c.inc   |   6 +
 target/riscv/tcg/insn_trans/trans_rvi.c.inc   |   6 +
 target/riscv/tcg/insn_trans/trans_rvv.c.inc   |  18 +-
 target/riscv/tcg/insn_trans/trans_rvzfh.c.inc |   6 +
 target/riscv/tcg/vector_helper.c              |  65 +++-
 tests/tcg/riscv64/Makefile.softmmu-target     |  22 ++
 tests/tcg/riscv64/test-zicclsm.S              | 368 ++++++++++++++++++
 11 files changed, 496 insertions(+), 24 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-zicclsm.S

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2.43.0