[PATCH v2 2/6] target/arm: Add FGWTE3_EL3 bit definitions
Richard Henderson <[email protected]>
| Newsgroups | gmane.comp.emulators.qemu |
|---|---|
| Message-ID | <[email protected]> |
Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpregs.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 34592679e4..2c9927b1d9 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -689,6 +689,30 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) +FIELD(FGWTE3_EL3, ACTLR_EL3, 0, 1) +FIELD(FGWTE3_EL3, AFSR0_EL3, 1, 1) +FIELD(FGWTE3_EL3, AFSR1_EL3, 2, 1) +FIELD(FGWTE3_EL3, AMAIR_EL3, 3, 1) +FIELD(FGWTE3_EL3, AMAIR2_EL3, 4, 1) +FIELD(FGWTE3_EL3, GCSCR_EL3, 5, 1) +FIELD(FGWTE3_EL3, GCSPR_EL3, 6, 1) +FIELD(FGWTE3_EL3, GPCCR_EL3, 7, 1) +FIELD(FGWTE3_EL3, GPTBR_EL3, 8, 1) +FIELD(FGWTE3_EL3, MAIR_EL3, 9, 1) +FIELD(FGWTE3_EL3, MAIR2_EL3, 10, 1) +FIELD(FGWTE3_EL3, MDCR_EL3, 11, 1) +FIELD(FGWTE3_EL3, MECID_RL_A_EL3, 12, 1) +FIELD(FGWTE3_EL3, MPAM3_EL3, 13, 1) +FIELD(FGWTE3_EL3, PIR_EL3, 14, 1) +FIELD(FGWTE3_EL3, SCTLR_EL3, 15, 1) +FIELD(FGWTE3_EL3, SCTLR2_EL3, 16, 1) +FIELD(FGWTE3_EL3, SPMROOTCR_EL3, 17, 1) +FIELD(FGWTE3_EL3, TCR_EL3, 18, 1) +FIELD(FGWTE3_EL3, TPIDR_EL3, 19, 1) +FIELD(FGWTE3_EL3, TTBR0_EL3, 20, 1) +FIELD(FGWTE3_EL3, VBAR_EL3, 21, 1) +FIELD(FGWTE3_EL3, GPCBW_EL3, 22, 1) + FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ /* Which fine-grained trap bit register to check, if any */ FIELD(FGT, TYPE, 10, 3) -- 2.43.0