Re: [PATCH 3/7] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207

Reviewed-by: Glenn Miles <[email protected]>

Thanks,

Glenn

On Wed, 2026-07-15 at 18:26 +0530, Chinmay Rath wrote:
> PPC2_LSQ_ISA207 is only ever set in the CPUPPCState's insns_flags2
> alongside PPC2_ISA207. Checks made by PPC2_LSQ_ISA207 could be
> replaced with PPC2_ISA207, hence rendering is useless and apt for
> removal. This patch does the same.
> 
> Signed-off-by: Chinmay Rath <[email protected]>
> ---
>  linux-user/ppc/elfload.c                   | 2 +-
>  target/ppc/cpu.h                           | 3 ---
>  target/ppc/cpu_init.c                      | 3 +--
>  target/ppc/cpu_init.h                      | 2 +-
>  target/ppc/translate/fixedpoint-impl.c.inc | 4 ++--
>  5 files changed, 5 insertions(+), 9 deletions(-)
> 
> diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c
> index 5c6065e08a..76ab9f43de 100644
> --- a/linux-user/ppc/elfload.c
> +++ b/linux-user/ppc/elfload.c
> @@ -116,7 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
>      do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
>  
>      GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
> -    GET_FEATURE2((PPC2_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> +    GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 |
>                    PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
>                    QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
>      GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index df1e943d8d..b3cd8d85df 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2577,8 +2577,6 @@ enum {
>      PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
>      /* ISA 2.06B floating point test instructions                            */
>      PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
> -    /* ISA 2.07 load/store quadword                                          */
> -    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
>      /* ISA 2.07 Altivec                                                      */
>      PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
>      /* PowerISA 2.07 Book3s specification                                    */
> @@ -2608,7 +2606,6 @@ enum {
>                          PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
>                          PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
>                          PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
> -                        PPC2_LSQ_ISA207 | \
>                          PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
>                          PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
>                          PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index be8b3c447d..9b0d19ba20 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6349,8 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
>      pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
>                          PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
>                          PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> -                        PPC2_FP_TST_ISA206 |
> -                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> +                        PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 |
>                          PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
>                          PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
>                          PPC2_BCDA_ISA206;
> diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h
> index 7dd587908e..6961007926 100644
> --- a/target/ppc/cpu_init.h
> +++ b/target/ppc/cpu_init.h
> @@ -18,7 +18,7 @@
>      (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |                 \
>       PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 |      \
>       PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 |                       \
> -     PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 |              \
> +     PPC2_ALTIVEC_207 | PPC2_ISA205 |                                \
>       PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL |    \
>       PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
>  
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 9c7c754db1..6e4c8c34b3 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -116,7 +116,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
>  
>      REQUIRE_INSNS_FLAGS(ctx, 64BX);
>  
> -    if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
> +    if (!prefixed && !(ctx->insns_flags2 & PPC2_ISA207)) {
>          /* lq and stq were privileged prior to V. 2.07 */
>          REQUIRE_SV(ctx);
>  
> @@ -280,7 +280,7 @@ TRANS64(STDCX, do_store_cond, MO_UQ);
>  static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a)
>  {
>      REQUIRE_64BIT(ctx);
> -    REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207);
> +    REQUIRE_INSNS_FLAGS2(ctx, ISA207);
>  #if defined(TARGET_PPC64)
>      TCGLabel *lfail = gen_new_label();
>      TCGv ea = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);