[PULL 00/38] tcg patch queue

The following changes since commit fa19879df1658f96ac07365fca8835b7decd6995:

  Merge tag 'pull-block-jobs-2026-08-17' of https://gitlab.com/vsementsov/qemu into staging (2026-08-17 15:37:53 -0700)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20260818

for you to fetch changes up to ff90861d1c4a1eda23d83cdb18c3647f2e2b0128:

  target/mips: Enable disassembly via capstone (2026-08-18 09:06:53 -0700)

----------------------------------------------------------------
accel/tcg: Allow overlapping reads in record_save
tcg/optimize: INDEX_op_mul is commutative
tcg/optimize: Fix s_mask computation for shifts
tcg: Defer tb_flush when initial thread region alloc fails
tcg: Add revbit{8,32,64} opcodes
tcg: Add integer min/max opcodes
disas: Updates for capstone v6

----------------------------------------------------------------
Ilya Chichkov (1):
      accel/tcg: Allow overlapping reads in record_save

Richard Henderson (37):
      tcg/optimize: INDEX_op_mul is commutative
      tcg/optimize: Fix s_mask computation for shifts
      tcg: Return success from tcg_region_alloc__locked
      tcg: Return success from tcg_region_alloc
      tcg: Defer tb_flush when initial thread region alloc fails
      tcg: Fix opcode dump for bswap
      tcg: Add tcg_gen_revbit{8,32,64}
      tcg: Simplify bswap/hswap expansion using bitswap
      target/arm: Use generic tcg_gen_revbit*
      target/loongarch: Use generic tcg_gen_revbit*
      target/mips: Expand octeon reflections inline
      target/riscv: Use generic tcg_gen_revbit8
      tcg: Add revbit{8,32,64} opcodes
      tcg/optimize: Handle revbit{8,32,64}
      tcg/aarch64: Implement revbit{32,64}
      tcg/loongarch64: Import REVBIT insns
      tcg/loongarch64: Implement revbit{8,32,64}
      util/cpuinfo-riscv: Detect Zbkb
      tcg/riscv64: Implement revbit8
      tests/tcg/loongarch64: Tidy test_bit.c
      tests/tcg/loongarch64: Add bitrev smoke tests
      tcg: Add integer min/max opcodes
      tcg/optimize: Handle min/max opcodes
      util/cpuinfo-aarch64: Detect FEAT_CSSC
      tcg/aarch64: Implement min/max with FEAT_CSSC
      target/riscv64: Implement min/max with Zbb
      tcg/aarch64: Implement ctpop with FEAT_CSSC
      tcg/aarch64: Use CTZ from FEAT_CSSC
      target/riscv: Improve riscv_has_ext
      disas/capstone: Allow for cap_insn_unit > length
      target/riscv: Enable disassembly via capstone
      target/sh4: Enable disassembly via capstone
      target/tricore: Enable disassembly via capstone
      target/loongarch: Enable disassembly via capstone
      target/s390x: Update capstone disassembly to v6
      target/m68k: Enable disassembly via capstone
      target/mips: Enable disassembly via capstone

 host/include/aarch64/host/cpuinfo.h             |   1 +
 host/include/riscv64/host/cpuinfo.h             |   1 +
 include/disas/capstone.h                        | 115 ++-
 include/tcg/tcg-op-common.h                     |   5 +
 include/tcg/tcg-op.h                            |   7 +
 include/tcg/tcg-opc.h                           |   7 +
 target/arm/tcg/helper-a64-defs.h                |   1 -
 target/arm/tcg/helper-defs.h                    |   1 -
 target/loongarch/tcg/helper.h                   |   4 -
 target/mips/helper.h                            |   7 -
 target/riscv/cpu.h                              |   2 +-
 target/riscv/helper.h                           |   1 -
 tcg/aarch64/tcg-target-con-set.h                |   2 +
 tcg/aarch64/tcg-target-con-str.h                |   2 +
 tcg/tcg-internal.h                              |   2 +-
 accel/tcg/translator.c                          |  14 +-
 disas/capstone.c                                |  29 +-
 target/arm/tcg/helper-a64.c                     |   5 -
 target/arm/tcg/op_helper.c                      |   5 -
 target/arm/tcg/translate-a64.c                  |   4 +-
 target/arm/tcg/translate.c                      |   2 +-
 target/loongarch/cpu.c                          |   8 +
 target/loongarch/tcg/op_helper.c                |  21 -
 target/m68k/cpu.c                               |  65 +-
 target/mips/cpu.c                               |  60 +-
 target/mips/tcg/octeon_crypto.c                 |  35 -
 target/mips/tcg/octeon_translate.c              |  49 +-
 target/riscv/cpu.c                              |  81 +-
 target/riscv/tcg/bitmanip_helper.c              |  15 -
 target/s390x/cpu.c                              |   4 +-
 target/sh4/cpu.c                                |  14 +
 target/tricore/cpu.c                            |  31 +
 tcg/optimize.c                                  | 142 +++-
 tcg/region.c                                    |  40 +-
 tcg/tcg-op.c                                    | 234 ++++--
 tcg/tcg.c                                       |  41 +-
 tests/tcg/i386/test-i386-opt-shr.c              |  21 +
 tests/tcg/loongarch64/test_bit.c                |  77 +-
 util/cpuinfo-aarch64.c                          |   2 +
 util/cpuinfo-riscv.c                            |  17 +-
 docs/devel/tcg-ops.rst                          |  28 +
 target/loongarch/tcg/insn_trans/trans_bit.c.inc |  13 +-
 target/riscv/tcg/insn_trans/trans_rvb.c.inc     |   2 +-
 tcg/aarch64/tcg-target.c.inc                    | 197 ++++-
 tcg/loongarch64/tcg-insn-defs.c.inc             | 960 +++++++++++++-----------
 tcg/loongarch64/tcg-target.c.inc                |  56 ++
 tcg/ppc64/tcg-target.c.inc                      |  28 +
 tcg/riscv64/tcg-target.c.inc                    |  79 ++
 tcg/s390x/tcg-target.c.inc                      |  28 +
 tcg/sparc64/tcg-target.c.inc                    |  28 +
 tcg/tci/tcg-target.c.inc                        |  28 +
 tcg/x86_64/tcg-target.c.inc                     |  28 +
 52 files changed, 1869 insertions(+), 780 deletions(-)
 create mode 100644 tests/tcg/i386/test-i386-opt-shr.c