Level sensitive ARM interrupts

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This patch makes arm interrupts level sensitive, as they are in hardware. The 
nirq and nfiq pins are no longer callbacks, but rather simple input pins. 
They are 'pulled' to high at processor invocation and reset. Their level is 
'sense()-ed' at the beginning of each step.

The patch file was taken from within the sid/component/cgen-cpu/arm7t 
directory.

This is necessary for proper operation of eCos, and for the ability to model 
interrupts as they occur in actual hardware.

Bob
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