Latency in cache hierarchies

"Mikael Starvik" <[email protected]>
Newsgroups gmane.comp.emulators.sid.devel
Message-ID <[email protected]>
Lets say you have a system with a L1-cache and a L2-cache.

In cache_component::read_line() the latency for the first read is saved as a
latency for the complete operation. This looks correct to me because it is
the first read that may trigger additional refills down the chain and has
the largest latency.

In cache_component::write_line() the latency for the last write is returned.
This makes me a bit confused. The first write may trigger dirty flushed down
the chain and should have the largest latency so why isn't that saved in the
same way as in read_line?

/Mikael
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