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gmane.comp.emulators.winex.cvs |
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Subject: winex/misc cpu.c,1.6,1.7Update of /var/lib/cvsd/cvsroot/winex/misc
In directory agravaine:/tmp/cvs-serv31420/misc
Modified Files:
cpu.c
Log Message:
Implement GetSystemInfo() and IsProcessorFeaturePresent() on MacOS X.
Index: cpu.c
===================================================================
RCS file: /var/lib/cvsd/cvsroot/winex/misc/cpu.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- cpu.c 27 Mar 2007 22:23:58 -0000 1.6
+++ cpu.c 30 Mar 2007 15:56:56 -0000 1.7
@@ -12,6 +12,11 @@
#include <string.h>
#include <stdio.h>
+#ifdef __APPLE__
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#endif
+
#include "winbase.h"
#include "winreg.h"
#include "winnt.h"
@@ -224,7 +229,104 @@
fclose (f);
}
memcpy(si,&cachedsi,sizeof(*si));
-#else /* linux */
+#elif defined(__APPLE__)
+ {
+ int iVal, i;
+ size_t ValSize;
+ char sVal[256];
+ long long lVal;
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.optional.mmx", &iVal, &ValSize, NULL, 0) == 0)
+ PF[PF_MMX_INSTRUCTIONS_AVAILABLE] = iVal;
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.optional.sse", &iVal, &ValSize, NULL, 0) == 0)
+ PF[PF_XMMI_INSTRUCTIONS_AVAILABLE] = iVal;
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.optional.sse2", &iVal, &ValSize, NULL, 0) == 0)
+ PF[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = iVal;
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.optional.sse3", &iVal, &ValSize, NULL, 0) == 0)
+ PF[PF_SSE3_INSTRUCTIONS_AVAILABLE] = iVal;
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.optional.floatingpoint", &iVal, &ValSize, NULL,
+ 0) == 0)
+ PF[PF_FLOATING_POINT_EMULATED] = !iVal;
+
+ ValSize = sizeof (sVal);
+ if (sysctlbyname ("machdep.cpu.features", &sVal, &ValSize, NULL, 0) == 0)
+ {
+ if (strstr (sVal, "TSC") != NULL)
+ PF[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
+
+ if (strstr (sVal, "PAE") != NULL)
+ PF[PF_PAE_ENABLED] = TRUE;
+
+ if (strstr (sVal, "CX8") != NULL)
+ PF[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
+
+ if (strstr (sVal, "CX16") != NULL)
+ PF[PF_COMPARE_EXCHANGE128] = TRUE;
+ }
+
+ ValSize = sizeof (int);
+ if (sysctlbyname ("hw.ncpu", &iVal, &ValSize, NULL, 0) == 0)
+ cachedsi.dwNumberOfProcessors = iVal;
+
+ for (i = 0; i < cachedsi.dwNumberOfProcessors; i++)
+ {
+ HKEY ProcKey;
+ int Family = 0, Model = 0, Stepping = 0;
+
+ sprintf (sVal, "%d", i);
+ RegCreateKeyA (hkey, sVal, &ProcKey);
+
+ ValSize = sizeof (sVal);
+ if (sysctlbyname ("machdep.cpu.vendor", &sVal, &ValSize, NULL, 0) == 0)
+ RegSetValueExA (ProcKey, "VendorIdentifier", 0, REG_SZ, (BYTE*)sVal,
+ strlen (sVal));
+
+ ValSize = sizeof (sVal);
+ if (sysctlbyname ("machdep.cpu.brand_string", &sVal, &ValSize, NULL,
+ 0) == 0)
+ RegSetValueExA (ProcKey, "ProcessorNameString", 0, REG_SZ,
+ (BYTE*)sVal, strlen (sVal));
+
+ ValSize = sizeof (int);
+ sysctlbyname ("machdep.cpu.family", &Family, &ValSize, NULL, 0);
+ ValSize = sizeof (int);
+ sysctlbyname ("machdep.cpu.model", &Model, &ValSize, NULL, 0);
+ ValSize = sizeof (int);
+ sysctlbyname ("machdep.cpu.stepping", &Stepping, &ValSize, NULL, 0);
+ sprintf (sVal, "x86 Family %d Model %d Stepping %d",
+ Family, Model, Stepping);
+ RegSetValueExA (ProcKey, "Identifier", 0, REG_SZ, (BYTE*)sVal,
+ strlen (sVal));
+
+ cachedsi.wProcessorRevision = Model << 8 | Stepping;
+
+ ValSize = sizeof (lVal);
+ if (sysctlbyname ("hw.cpufrequency", &lVal, &ValSize, NULL, 0) == 0)
+ {
+ iVal = (int)(lVal / 1000000);
+ RegSetValueExA (ProcKey, "~MHz", 0, REG_DWORD, (BYTE *)&iVal, 4);
+ }
+
+ RegCloseKey (ProcKey);
+
+ cachedsi.dwActiveProcessorMask |= 1 << i;
+ }
+
+ cachedsi.dwProcessorType = PROCESSOR_INTEL_PENTIUM;
+ cachedsi.wProcessorLevel = 5;
+
+ memcpy(si,&cachedsi,sizeof(*si));
+ }
+#else
FIXME("not yet supported on this system !!\n");
/* Fill in some stuff by default on an x86 */
@@ -242,7 +344,7 @@
RegCloseKey(xhkey);
if (hkey)
RegCloseKey(hkey);
- TRACE("<- CPU arch %d, res'd %d, pagesize %ld, minappaddr %p, maxappaddr %p, act.cpumask %08lx, numcpus %ld, CPU type %ld, allocgran. %ld, CPU level %d, CPU rev %d\n", si->u.s.wProcessorArchitecture, si->u.s.wReserved, si->dwPageSize, si->lpMinimumApplicationAddress, si->lpMaximumApplicationAddress, si->dwActiveProcessorMask, si->dwNumberOfProcessors, si->dwProcessorType, si->dwAllocationGranularity, si->wProcessorLevel, si->wProcessorRevision);
+ TRACE("<- CPU arch %d, res'd %d, pagesize %ld, minappaddr %p, maxappaddr %p, act.cpumask %08lx, numcpus %ld, CPU type %ld, allocgran. %ld, CPU level %d, CPU rev 0x%hx\n", si->u.s.wProcessorArchitecture, si->u.s.wReserved, si->dwPageSize, si->lpMinimumApplicationAddress, si->lpMaximumApplicationAddress, si->dwActiveProcessorMask, si->dwNumberOfProcessors, si->dwProcessorType, si->dwAllocationGranularity, si->wProcessorLevel, si->wProcessorRevision);
}
/***********************************************************************