Re: [PATCH] cipher:riscv: gate Zvkned AES backend on VLEN == 128

On 2026-05-06 12:51, Michael Neuling wrote:
> Jussi,
> 
>> Thanks for checking this out and for the reproducer. I tested with 
>> clang
>> and same problem persists, __riscv_vset_v_u32m1_u32m4 usage must be
>> wrong. I'll check for proper fix.
> 
> Thanks! I'm happy to test if you have something.
> 
> If it helps, Claude had a go at a fix that works for me:
>   
> https://github.com/mikey/libgcrypt/commit/c22ff9747c4e7b8b77360eb29b7a8cd91cee1a00

Thanks. I'm considering either vslideup or vcreate+vgather method for
quick fix to avoid memory writing+reading.

Then for actual fix, implementation would need to be checked if 4xM1->M4
transitions could be avoided altogether.

-Jussi