[PATCH] rijndael-vp-riscv: clear upper half when moving 128-bit to 256-bit

* cipher/rijndael-vp-riscv.c (movdqa128_256): Clear high 128-bit half
of target 256-bit vector register.
--

movdqa128_256 left high 128-bit half of target register
uninitialized. With vector tail-agnostic all-ones policy
(as with QEMU_CPU "max,vlen=256,rvv_ta_all_1s=true") upper
half read back as all-ones and corrupted OCB checksum.
Zero it explicitly.

Signed-off-by: Jussi Kivilinna <[email protected]>
---
 cipher/rijndael-vp-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cipher/rijndael-vp-riscv.c b/cipher/rijndael-vp-riscv.c
index 24ae3a7c..7a1da94f 100644
--- a/cipher/rijndael-vp-riscv.c
+++ b/cipher/rijndael-vp-riscv.c
@@ -230,7 +230,7 @@ typedef vuint8m1_t __m256i;
 
 #define movdqa256(a, o)         (o = (a))
 
-#define movdqa128_256(a, o)     (o = (a))
+#define movdqa128_256(a, o)     (o = __riscv_vslideup_vx_u8m1((a), __riscv_vmv_v_x_u8m1(0, 16), 16, 32))
 #define movdqa256_128(a, o)     (o = (a))
 
 #define movdqa256_memld(a, o)   (o = __riscv_vle8_v_u8m1((const void *)(a), 32))
-- 
2.53.0