xserver/hw/kdrive/ati ati_dri.c,1.11,1.12 ati_reg.h,1.9,1.10

Committed by: anholt

Update of /cvs/xserver/xserver/hw/kdrive/ati
In directory gabe:/tmp/cvs-serv27702/hw/kdrive/ati

Modified Files:
	ati_dri.c ati_reg.h 
Log Message:
Unbreak the AGP DRI case.  That was quite a pile of broken code.


Index: ati_dri.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_dri.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- ati_dri.c	12 Sep 2004 23:01:24 -0000	1.11
+++ ati_dri.c	19 Sep 2004 10:57:31 -0000	1.12
@@ -241,13 +241,8 @@
 	unsigned char *mmio = atic->reg_base;
 	unsigned long mode;
 	int           ret;
-	unsigned long agpBase;
 	CARD32        cntl, chunk;
 
-	/* AGP DRI seems broken on my R128, not sure why. */
-	if (!atic->is_radeon)
-		return FALSE;
-
 	if (drmAgpAcquire(atic->drmFd) < 0) {
 		ErrorF("[agp] AGP not available\n");
 		return FALSE;
@@ -255,30 +250,21 @@
 
 	ATIDRIInitGARTValues(pScreen);
 
-	/* Modify the mode if the default mode is not appropriate for this
-	 * particular combination of graphics card and AGP chipset.
-	 */
-
-	/* XXX: Disable fast writes? */
-
 	mode = drmAgpGetMode(atic->drmFd);
-	if (mode > 4)
-		mode = 4;
-	/* Set all mode bits below the chosen one so fallback can happen */
-	mode = (mode * 2) - 1;
+	if (atic->is_radeon) {
+		mode &= ~RADEON_AGP_MODE_MASK;
+		mode |= RADEON_AGP_1X_MODE;
+	} else {
+		mode &= ~R128_AGP_MODE_MASK;
+		mode |= R128_AGP_1X_MODE;
+	}
 
 	if (drmAgpEnable(atic->drmFd, mode) < 0) {
 		ErrorF("[agp] AGP not enabled\n");
 		drmAgpRelease(atic->drmFd);
 		return FALSE;
 	}
-
-	/* Workaround for some hardware bugs */
-	if (atic->is_r100) {
-		cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
-		MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl |
-		    RADEON_PENDING_SLOTS_VAL | RADEON_PENDING_SLOTS_SEL);
-	}
+	ErrorF("[agp] Mode 0x%08x selected\n", drmAgpGetMode(atic->drmFd));
 
 	if ((ret = drmAgpAlloc(atic->drmFd, atis->gartSize * 1024 * 1024, 0,
 	    NULL, &atis->agpMemHandle)) < 0) {
@@ -317,27 +303,29 @@
 	    (drmAddressPtr)&atis->gartTex, "AGP texture map"))
 		return FALSE;
 
-	/* Initialize radeon/r128 AGP registers */
-	cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
-	cntl &= ~ATI_AGP_APER_SIZE_MASK;
-	switch (atis->gartSize) {
-	case 256: cntl |= ATI_AGP_APER_SIZE_256MB; break;
-	case 128: cntl |= ATI_AGP_APER_SIZE_128MB; break;
-	case  64: cntl |= ATI_AGP_APER_SIZE_64MB;  break;
-	case  32: cntl |= ATI_AGP_APER_SIZE_32MB;  break;
-	case  16: cntl |= ATI_AGP_APER_SIZE_16MB;  break;
-	case   8: cntl |= ATI_AGP_APER_SIZE_8MB;   break;
-	case   4: cntl |= ATI_AGP_APER_SIZE_4MB;   break;
-	default:
-		ErrorF("[agp] Illegal aperture size %d kB\n", atis->gartSize *
-		    1024);
+	if (atic->is_r100) {
+		/* Workaround for some hardware bugs */
+		cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
+		MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl |
+		    RADEON_PENDING_SLOTS_VAL | RADEON_PENDING_SLOTS_SEL);
+	} else if (!atic->is_radeon) {
+		cntl = MMIO_IN32(mmio, ATI_REG_AGP_CNTL);
+		cntl &= ~R128_AGP_APER_SIZE_MASK;
+		switch (atis->gartSize) {
+		case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
+		case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
+		case  64: cntl |= R128_AGP_APER_SIZE_64MB;  break;
+		case  32: cntl |= R128_AGP_APER_SIZE_32MB;  break;
+		case  16: cntl |= R128_AGP_APER_SIZE_16MB;  break;
+		case   8: cntl |= R128_AGP_APER_SIZE_8MB;   break;
+		case   4: cntl |= R128_AGP_APER_SIZE_4MB;   break;
+		default:
+			ErrorF("[agp] Illegal aperture size %d kB\n", atis->gartSize *
+			    1024);
 		return FALSE;
-	}
-	agpBase = drmAgpBase(atic->drmFd);
-	MMIO_OUT32(mmio, ATI_REG_AGP_BASE, agpBase); 
-	MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl);
+		}
+		MMIO_OUT32(mmio, ATI_REG_AGP_CNTL, cntl);
 
-	if (!atic->is_radeon) {
 		/* Disable Rage 128 PCIGART registers */
 		chunk = MMIO_IN32(mmio, R128_REG_BM_CHUNK_0_VAL);
 		chunk &= ~(R128_BM_PTR_FORCE_TO_PCI |
@@ -349,6 +337,8 @@
 		MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
 	}
 
+	MMIO_OUT32(mmio, ATI_REG_AGP_BASE, drmAgpBase(atic->drmFd)); 
+
 	return TRUE;
 }
 

Index: ati_reg.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_reg.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- ati_reg.h	14 Sep 2004 06:26:54 -0000	1.9
+++ ati_reg.h	19 Sep 2004 10:57:31 -0000	1.10
@@ -104,16 +104,16 @@
 #define ATI_REG_AGP_BASE			0x0170
 
 #define ATI_REG_AGP_CNTL			0x0174
-# define ATI_AGP_APER_SIZE_256MB		(0x00 << 0)
-# define ATI_AGP_APER_SIZE_128MB		(0x20 << 0)
-# define ATI_AGP_APER_SIZE_64MB			(0x30 << 0)
-# define ATI_AGP_APER_SIZE_32MB			(0x38 << 0)
-# define ATI_AGP_APER_SIZE_16MB			(0x3c << 0)
-# define ATI_AGP_APER_SIZE_8MB			(0x3e << 0)
-# define ATI_AGP_APER_SIZE_4MB			(0x3f << 0)
-# define ATI_AGP_APER_SIZE_MASK			(0x3f << 0)
-#define RADEON_PENDING_SLOTS_VAL		0x00060000
-#define RADEON_PENDING_SLOTS_SEL		0x00080000
+# define R128_AGP_APER_SIZE_256MB		(0x00 << 0)
+# define R128_AGP_APER_SIZE_128MB		(0x20 << 0)
+# define R128_AGP_APER_SIZE_64MB		(0x30 << 0)
+# define R128_AGP_APER_SIZE_32MB		(0x38 << 0)
+# define R128_AGP_APER_SIZE_16MB		(0x3c << 0)
+# define R128_AGP_APER_SIZE_8MB			(0x3e << 0)
+# define R128_AGP_APER_SIZE_4MB			(0x3f << 0)
+# define R128_AGP_APER_SIZE_MASK		(0x3f << 0)
+# define RADEON_PENDING_SLOTS_VAL		0x00060000
+# define RADEON_PENDING_SLOTS_SEL		0x00080000
 
 #define R128_REG_PCI_GART_PAGE			0x017c
 
@@ -294,9 +294,22 @@
 # define ATI_CAP_ID_NULL			0x0000 /* End of capability list */
 # define ATI_CAP_ID_AGP				0x0002 /* AGP capability ID */
 
+#define R128_REG_AGP_STATUS			0x0f54 /* PCI */
+# define R128_AGP_1X_MODE			0x01
+# define R128_AGP_2X_MODE			0x02
+# define R128_AGP_4X_MODE			0x04
+# define R128_AGP_MODE_MASK			0x07
+
 #define R128_REG_AGP_COMMAND			0x0f58
 # define R128_AGP_ENABLE			(1 << 8)
 
+#define RADEON_REG_AGP_STATUS			0x0f5c /* PCI */
+# define RADEON_AGP_1X_MODE			0x01
+# define RADEON_AGP_2X_MODE			0x02
+# define RADEON_AGP_4X_MODE			0x04
+# define RADEON_AGP_FW_MODE			0x10
+# define RADEON_AGP_MODE_MASK			0x17
+
 #define RADEON_REG_AGP_COMMAND			0x0f60
 # define RADEON_AGP_ENABLE			(1 << 8)