xserver/hw/kdrive/ati ati_draw.c, 1.26, 1.27 ati_reg.h, 1.11, 1.12 radeon_composite.c, 1.13, 1.14

Eric Anholt <xserver-commit-u7BhqnqprCWvj1b/[email protected]>
Newsgroups gmane.comp.freedesktop.xserver.cvs
Message-ID <[email protected]> 
Committed by: anholt

Update of /cvs/xserver/xserver/hw/kdrive/ati
In directory gabe:/tmp/cvs-serv610/hw/kdrive/ati

Modified Files:
	ati_draw.c ati_reg.h radeon_composite.c 
Log Message:
Back out the previous day's broken R200 "fix" -- the same number of
coords are always emitted.  Fix the real problem, which was not enough
regs being initialized in ati_draw.c.  Fix a typo that was resulting in
alpha coming out as 0 * src or 0 * broken instead of src * 1 or src *
mask.  Assign the blending results to R0, as appears to be necessary.
Unbreak the dst-alpha-blend-with-no-dst-alpha code.  Yow.  And set the
right DMA count for the r200 traps code.


Index: ati_draw.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_draw.c,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- ati_draw.c	21 Dec 2004 09:51:47 -0000	1.26
+++ ati_draw.c	22 Dec 2004 18:39:41 -0000	1.27
@@ -162,7 +162,11 @@
 			    RADEON_TEX1_W_ROUTING_USE_W0);
 			END_DMA();
 		} else {
-			BEGIN_DMA(8);
+			BEGIN_DMA(16);
+			OUT_REG(R200_REG_SE_VAP_CNTL_STATUS, 0 /*RADEON_TCL_BYPASS*/);
+			OUT_REG(R200_REG_PP_CNTL_X, 0);
+			OUT_REG(R200_REG_PP_TXMULTI_CTL_0, 0);
+			OUT_REG(R200_REG_SE_VTX_STATE_CNTL, 0);
 			OUT_REG(R200_REG_RE_CNTL, 0);
 			/* XXX: VTX_ST_DENORMALIZED is illegal for the case of
 			 * repeating textures.

Index: ati_reg.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_reg.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- ati_reg.h	20 Sep 2004 03:12:00 -0000	1.11
+++ ati_reg.h	22 Dec 2004 18:39:41 -0000	1.12
@@ -1233,6 +1233,7 @@
 # define R200_VTX_W0_NORMALIZE			0x00000800
 # define R200_VTX_ST_DENORMALIZED		0x00001000
 
+#define R200_REG_SE_VAP_CNTL_STATUS		0x2140
 #define RADEON_REG_SE_CNTL_STATUS		0x2140
 # define RADEON_VC_NO_SWAP			(0 << 0)
 # define RADEON_VC_16BIT_SWAP			(1 << 0)
@@ -1240,6 +1241,8 @@
 # define RADEON_VC_HALF_DWORD_SWAP		(3 << 0)
 # define RADEON_TCL_BYPASS			(1 << 8)
 
+#define R200_REG_SE_VTX_STATE_CNTL		0x2180
+
 #define RADEON_REG_RE_TOP_LEFT			0x26c0
 
 #define R200_REG_RE_AUX_SCISSOR_CNTL		0x26f0
@@ -1374,6 +1377,9 @@
 #define R200_REG_PP_TXSIZE_0			0x2c0c /* NPOT only */
 #define R200_REG_PP_TXPITCH_0			0x2c10 /* NPOT only */
 #define R200_REG_PP_BORDER_COLOR_0		0x2c14
+#define R200_REG_PP_TXMULTI_CTL_0		0x2c1c
+
+#define R200_REG_PP_CNTL_X			0x2cc4
 
 #define R200_PP_TXOFFSET_0			0x2d00
 #define R200_PP_TXOFFSET_1			0x2d18
@@ -1419,6 +1425,7 @@
 #define R200_PP_CUBIC_OFFSET_F4_5		0x2d88
 #define R200_PP_CUBIC_OFFSET_F5_5		0x2d8c
 
+/* AKA PIXSHADER_I0_C0 */
 #define R200_REG_PP_TXCBLEND_0			0x2f00
 # define R200_TXC_ARG_A_ZERO			(0)
 # define R200_TXC_ARG_A_CURRENT_COLOR		(2)
@@ -1519,6 +1526,7 @@
 # define R200_TXC_OP_DOT2_ADD			(7 << 28)
 # define R200_TXC_OP_MASK			(7 << 28)
 
+/* AKA PIXSHADER_I0_C1 */
 #define R200_REG_PP_TXCBLEND2_0			0x2f04
 # define R200_TXC_TFACTOR_SEL_SHIFT		0
 # define R200_TXC_TFACTOR_SEL_MASK		0x7
@@ -1566,6 +1574,7 @@
 # define R200_TXC_REPL_ARG_C_SHIFT		30
 # define R200_TXC_REPL_ARG_C_MASK		(3 << 30)
 
+/* AKA PIXSHADER_I0_A0 */
 #define R200_REG_PP_TXABLEND_0			0x2f08
 # define R200_TXA_ARG_A_ZERO			(0)
 # define R200_TXA_ARG_A_CURRENT_ALPHA		(2) /* guess */
@@ -1663,6 +1672,7 @@
 # define R200_TXA_OP_CONDITIONAL		(6 << 28)
 # define R200_TXA_OP_MASK			(7 << 28)
 
+/* AKA PIXSHADER_I0_A1 */
 #define R200_REG_PP_TXABLEND2_0			0x2f0c
 # define R200_TXA_TFACTOR_SEL_SHIFT		0
 # define R200_TXA_TFACTOR_SEL_MASK		0x7

Index: radeon_composite.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/radeon_composite.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- radeon_composite.c	21 Dec 2004 09:51:47 -0000	1.13
+++ radeon_composite.c	22 Dec 2004 18:39:41 -0000	1.14
@@ -407,7 +407,7 @@
 	}
 	txformat = R200TexFormats[i].card_fmt;
 	if (R200TexFormats[i].byte_swap)
-		txoffset |= RADEON_TXO_ENDIAN_BYTE_SWAP;
+		txoffset |= R200_TXO_ENDIAN_BYTE_SWAP;
 
 	if (pPict->repeat) {
 		txformat |= ATILog2(w) << R200_TXFORMAT_WIDTH_SHIFT;
@@ -433,8 +433,8 @@
 	OUT_RING(txformat);
 	OUT_RING(0);
 	OUT_RING((pPix->drawable.width - 1) |
-	    ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); /* XXX */
-	OUT_RING(txpitch - 32); /* XXX */
+	    ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
+	OUT_RING(txpitch - 32);
 	END_DMA();
 
 	BEGIN_DMA(2);
@@ -528,7 +528,7 @@
 	OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
 	OUT_REG(R200_REG_SE_VTX_FMT_1,
 	    (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
-	    (pMask != NULL) ? (2 << R200_VTX_TEX1_COMP_CNT_SHIFT) : 0);
+	    (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
 
 	OUT_REG(RADEON_REG_RB3D_COLORPITCH, dst_pitch >> pixel_shift);
 
@@ -546,7 +546,7 @@
 		cblend |= R200_TXC_ARG_A_ZERO;
 	else
 		cblend |= R200_TXC_ARG_A_R0_COLOR;
-	ablend |= R200_TXA_ARG_B_R0_ALPHA;
+	ablend |= R200_TXA_ARG_A_R0_ALPHA;
 
 	if (pMask) {
 		if (pMaskPicture->componentAlpha &&
@@ -562,20 +562,25 @@
 
 	OUT_REG(R200_REG_PP_TXCBLEND_0, cblend);
 	OUT_REG(R200_REG_PP_TXABLEND_0, ablend);
-	OUT_REG(R200_REG_PP_TXCBLEND2_0, 0);
-	OUT_REG(R200_REG_PP_TXABLEND2_0, 0);
+	OUT_REG(R200_REG_PP_TXCBLEND2_0,
+	    R200_TXC_CLAMP_0_1 |
+	    R200_TXC_OUTPUT_REG_R0);
+	OUT_REG(R200_REG_PP_TXABLEND2_0,
+	    R200_TXA_CLAMP_0_1 |
+	    R200_TXA_OUTPUT_REG_R0);
 
 	/* Op operator. */
 	blendcntl = RadeonBlendOp[op].blend_cntl;
 	if (PICT_FORMAT_A(pDstPicture->format) == 0 &&
 	    RadeonBlendOp[op].dst_alpha) {
-		blendcntl &= ~RADEON_SBLEND_MASK;
 		if ((blendcntl & RADEON_SBLEND_MASK) ==
 		    RADEON_SBLEND_GL_DST_ALPHA)
-			blendcntl |= RADEON_SBLEND_GL_ONE;
+			blendcntl = (blendcntl & ~RADEON_SBLEND_MASK) |
+			    RADEON_SBLEND_GL_ONE;
 		else if ((blendcntl & RADEON_SBLEND_MASK) ==
 		    RADEON_SBLEND_GL_INV_DST_ALPHA)
-			blendcntl |= RADEON_SBLEND_GL_ZERO;
+			blendcntl = (blendcntl & ~RADEON_SBLEND_MASK) |
+			    RADEON_SBLEND_GL_ZERO;
 	}
 	OUT_REG(RADEON_REG_RB3D_BLENDCNTL, blendcntl);
 	END_DMA();
@@ -742,15 +747,15 @@
 		OUT_RING(0x01000000);
 		END_DMA();
 	} else if (atic->is_r200) {
-		BEGIN_DMA(12);
+		BEGIN_DMA(14);
 		OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
 		OUT_REG(R200_REG_SE_VTX_FMT_1, 0);
 		OUT_REG(R200_REG_PP_TXCBLEND_0,
 		    R200_TXC_ARG_C_TFACTOR_COLOR);
 		OUT_REG(R200_REG_PP_TXABLEND_0,
 		    R200_TXA_ARG_C_TFACTOR_ALPHA);
-		OUT_REG(R200_REG_PP_TXCBLEND2_0, 0);
-		OUT_REG(R200_REG_PP_TXABLEND2_0, 0);
+		OUT_REG(R200_REG_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
+		OUT_REG(R200_REG_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
 		OUT_REG(RADEON_REG_PP_TFACTOR_0, 0x01000000);
 		END_DMA();
 	}
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