xserver/hw/kdrive/ati ati_dma.c,1.5,1.6 ati_reg.h,1.12,1.13

Committed by: anholt

Update of /cvs/xserver/xserver/hw/kdrive/ati
In directory gabe:/tmp/cvs-serv14049/hw/kdrive/ati

Modified Files:
	ati_dma.c ati_reg.h 
Log Message:
Make R200 PDMA work -- primary queue sizes are now 9 bits, not 8.


Index: ati_dma.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_dma.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- ati_dma.c	12 Sep 2004 20:31:39 -0000	1.5
+++ ati_dma.c	20 Jan 2005 01:09:48 -0000	1.6
@@ -271,8 +271,12 @@
 		int csq_stat, diff;
 	
 		csq_stat = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT);
-		diff = ((csq_stat & RADEON_CSQ_WPTR_PRIMARY_MASK) >> 8) - 
-		    (csq_stat & RADEON_CSQ_RPTR_PRIMARY_MASK);
+		if (atic->is_r200)
+			diff = ((csq_stat & R200_CSQ_WPTR_PRIMARY_MASK) >> 9) - 
+			    (csq_stat & R200_CSQ_RPTR_PRIMARY_MASK);
+		else
+			diff = ((csq_stat & RADEON_CSQ_WPTR_PRIMARY_MASK) >> 8) - 
+			    (csq_stat & RADEON_CSQ_RPTR_PRIMARY_MASK);
 	
 		if (diff < 0)
 			return -diff;
@@ -762,13 +766,19 @@
 	ATICardInfo(pScreenPriv);
 	char *mmio = atic->reg_base;
 
-	if (atic->is_r200 || atic->is_r300)
+	if (atic->is_r300)
 		return FALSE;
 
 	ATIUploadMicrocode(atis);
 	ATIEngineReset(atis);
 
-	if (atic->is_radeon) {
+	if (atic->is_r200) {
+		MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
+		    RADEON_CSQ_PRIPIO_INDDIS);
+		atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
+		    R200_CSQ_CNT_PRIMARY_MASK;
+		MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
+	} if (atic->is_radeon) {
 		MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
 		    RADEON_CSQ_PRIPIO_INDDIS);
 		atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
@@ -863,7 +873,13 @@
 	MMIO_OUT32(mmio, ATI_REG_CCE_RPTR, atis->ring_read);
 	MMIO_OUT32(mmio, ATI_REG_CCE_RPTR_ADDR, 0 /* XXX? */);
 
-	if (atic->is_radeon) {
+	if (atic->is_r200) {
+		MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
+		    RADEON_CSQ_PRIBM_INDBM);
+		atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
+		    R200_CSQ_CNT_PRIMARY_MASK;
+		MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
+	} else if (atic->is_radeon) {
 		MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
 		    RADEON_CSQ_PRIBM_INDBM);
 		atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &

Index: ati_reg.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_reg.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- ati_reg.h	22 Dec 2004 18:39:41 -0000	1.12
+++ ati_reg.h	20 Jan 2005 01:09:48 -0000	1.13
@@ -244,6 +244,8 @@
 #define RADEON_REG_CP_CSQ_CNTL			0x0740
 # define RADEON_CSQ_CNT_PRIMARY_MASK		0x000000ff
 # define RADEON_CSQ_CNT_INDIRECT_MASK		0x0000ff00
+# define R200_CSQ_CNT_PRIMARY_MASK		0x000001ff
+# define R200_CSQ_CNT_INDIRECT_MASK		0x0003fe00
 # define RADEON_CSQ_PRIDIS_INDDIS		(0 << 28)
 # define RADEON_CSQ_PRIPIO_INDDIS		(1 << 28)
 # define RADEON_CSQ_PRIBM_INDDIS		(2 << 28)
@@ -274,6 +276,8 @@
 # define RADEON_CSQ_WPTR_PRIMARY_MASK		(0xff <<  8)
 # define RADEON_CSQ_RPTR_INDIRECT_MASK		(0xff << 16)
 # define RADEON_CSQ_WPTR_INDIRECT_MASK		(0xff << 24)
+# define R200_CSQ_RPTR_PRIMARY_MASK		(0x1ff <<  0)
+# define R200_CSQ_WPTR_PRIMARY_MASK		(0x1ff <<  9)
 
 #define R128_REG_PM4_MICRO_CNTL			0x07fc
 # define R128_PM4_MICRO_FREERUN			(1 << 30)