[Bug target/126382] [16/17 regression] Incorrect compiler generated code resulting in seg fault - hoisted tls() in x86_cse caused register clobbering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126382

--- Comment #4 from Reshma Roy <Reshma.Roy at amd dot com> ---
(In reply to H.J. Lu from comment #3)
> Created attachment 65121 [details]
> A patch
> 
> Try this.

Thanks for the patch, it fixes the issue. 

Just to understand this better: the problem was that %r10 is live at the entry
block but has no reaching definition yet (its defined later, in the
prologue-epilog pass later in the pass pipeline), so its missing from
DF_LIVE_IN. Could other registers hit the same problem, live across the
insertion point, but defined later? If so, would using DF_LR_IN for the whole
check be a general fix, since it's a superset of DF_LIVE_IN?