[Bug tree-optimization/126385] aarch64: integer GEMV reduction vectorized as one serial dot-product chain instead of parallel accumulators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126385

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2026-07-24
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
enhancing outer loop vectorization would get you unroll-and-jam.

t.c:12:21: note:   === vect_analyze_data_ref_accesses ===
t.c:12:21: note:   grouped access in outer loop.
t.c:12:21: missed:   not vectorized: complicated access pattern.
t.c:16:24: missed:   not vectorized: complicated access pattern.
t.c:12:21: missed:  bad data access.

That's the weights[i * IN_DIM + j] access.  Outer loop vectorization of
the following variant works fine:

  for (int i = 0; i < OUT_DIM; ++i)
    {
      int32_t s = biases[i];
      for (int j = 0; j < IN_DIM; ++j)
        s += (int32_t) weights[/*i * IN_DIM +*/ j] * (int32_t) input[j];
      out[i] = s;
    }

the i * IN_DIM biasing effectively turns this into a gather, [j] indexing
is a splat.

Your unroll-and-jam input would result in the same if we use a SLP
reduction vectorization (a single vector IV), instead of doing N
separate reduction vectorizations which is what you want I think.