[Bug target/125746] [16/17 Regression] ICE in gen_rtx_SUBREG, at emit-rtl.cc:1043 since r16-718

"dimitar at gcc dot gnu.org via Gcc-bugs" <[email protected]> Fri, 31 Jul 2026 11:08:42 +0000

Newsgroups	gmane.comp.gcc.bugs
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125746

--- Comment #6 from Dimitar Dimitrov <dimitar at gcc dot gnu.org> ---
Created attachment 65194
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=65194&action=edit
proposed-fix-20260731.patch

My proposed-fix-20260615.patch is too naive. Rejecting all modes not
compatible with SSE1 also prevents split patterns which help move data between
SSE and normal registers. This caused regression fail for case
gcc.target/i386/pr31486.c

Next I tried to reject only 8-bit and 16-bit modes for SSE1 (see attached
proposed-fix-20260731.patch).
It passes bootstrap and has no regressions for c and c++. But I noticed a
small code quality regression when comparing builds of ffmpeg with and without
this patch.  I traced it to ix86_modes_tieable_p calling
"ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2)",
hence preventing usage of SSE1 registers and causing a slight increase in
register spilling.