[Bug target/126556] [15/16/17 Regression] ICE at -O2 on aarch64 during RTL pass: combine

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126556

--- Comment #2 from Drea Pinski <pinskia at gcc dot gnu.org> ---
But in GCC 14 combine was also with a very similar thing:
```
Trying 11 -> 12:
   11: cc:CC=cmp(r109:SI,0)
      REG_DEAD r109:SI
   12: r110:SI=cc:CC>0
      REG_DEAD cc:CC
Successfully matched this instruction:
(set (reg:SI 110 [ _2 ])
    (const_int 0 [0]))
allowing combination of insns 11 and 12
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 11.
deferring deletion of insn with uid = 10.
modifying insn i3    12: r110:SI=0
deferring rescan insn with uid = 12.
```

Somehow the mode QI came in but the none of the insns uses QI mode. So it must
be left over from a previous insns.