[Bug target/126619] [17 Regression] Slowdown of s116 from TSVC on x86_64 since r17-2876-gf0bd50e8317926

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126619

--- Comment #3 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
(In reply to Roger Sayle from comment #1)
> Many thanks for benchmarking, reporting this problem and reducing a testcase.
> Yes, there's a serious regression with V4SF, not (intrinsically) in the RTL
> expansion which uses the same insructions as before
> "unpcklps+unpcklps+movlhps"
> but in the book-keeping/register allocation.
> 
> This is seen in the fabcd case for v4sf.
> 
> Before:
>         unpcklps        %xmm3, %xmm2
>         unpcklps        %xmm1, %xmm0
>         movlhps %xmm2, %xmm0
>         ret
> 
> After:
>         movd    %xmm0, %eax
>         movd    %eax, %xmm0
>         movd    %xmm1, %eax
>         movd    %eax, %xmm1
>         movd    %xmm2, %eax
>         movd    %eax, %xmm2
>         movd    %xmm3, %eax
>         unpcklps        %xmm1, %xmm0
>         movd    %eax, %xmm3
>         unpcklps        %xmm3, %xmm2
>         movlhps %xmm2, %xmm0
>         ret
> 
> I'm guessing there's a missing SF/V4SF case/variant in a define_insn that
> exists for the corresponding SI/V4SI.
> Investigating...

Constructing {a,b,c,d} recursively materializes four {x,0,0,0} vectors. SSE2
gains eight movd instructions; AVX2 gains four vinsertps, while the original
emits only three shuffles. I think we'd better to restore original behavior?

--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -19291,21 +19291,7 @@ ix86_expand_vector_init_v4sf (rtx target, rtx *ops)
       emit_insn (gen_rtx_SET (target, gen_rtx_IOR (V4SFmode, tmp1, tmp2)));
     }
   else
-    {
-      rtx tmp1 = gen_reg_rtx (V4SFmode);
-      rtx tmp2 = gen_reg_rtx (V4SFmode);
-      vars[0] = ops[0];
-      vars[1] = ops[1];
-      vars[2] = CONST0_RTX (SFmode);
-      vars[3] = CONST0_RTX (SFmode);
-      ix86_expand_vector_init_v4sf (tmp1, vars);
-      vars[0] = ops[2];
-      vars[1] = ops[3];
-      ix86_expand_vector_init_v4sf (tmp2, vars);
-      emit_insn (gen_sse_shufps_v4sf (target, tmp1, tmp2,
-                                     const0_rtx, const1_rtx,
-                                     GEN_INT (4), GEN_INT (5)));
-    }
+    ix86_expand_vector_init_concat (V4SFmode, target, ops, 4);
 }