[Bug c++/126803] New: GCC fails to process <riscv_vector.h> when targeting the valid zve32f_zvl256b ISA combination in C++.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126803

            Bug ID: 126803
           Summary: GCC fails to process <riscv_vector.h> when targeting
                    the valid zve32f_zvl256b ISA combination in C++.
           Product: gcc
           Version: 15.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c++
          Assignee: unassigned at gcc dot gnu.org
          Reporter: cmiao at nvidia dot com
  Target Milestone: ---

Minimal Reproducer

#include <riscv_vector.h>

vfloat32m1_t identity(vfloat32m1_t value)
{
    return value;
}

riscv64-unknown-elf-g++ \
  -std=c++17 \
  -march=rv64imafc_zve32f_zvl256b \
  -mabi=lp64f \
  -c test.cpp

Observed Behavior

Compilation fails while GCC processes:

#pragma riscv intrinsic "vector"

Typical diagnostic:

error: ambiguating new declaration of
'vfloat16m4_t __riscv_vluxei8(const _Float16 *,
                               vuint8m2_t,
                               unsigned long)'

note: old declaration
'vfloat16mf4_t __riscv_vluxei8(const _Float16 *,
                               vuint8mf8_t,
                               unsigned long)'

The failure occurs before compiling any user RVV operation. The reproducer uses
only an FP32 vector type, but GCC fails while registering unrelated FP16/BF16
and indexed-load intrinsic overloads.

Expected Behavior

zve32f_zvl256b is a valid ISA combination. Including <riscv_vector.h> and using
supported FP32 RVV types should compile successfully. Unsupported intrinsic
variants must not produce conflicting declarations.

Affected Versions

GCC 14.2.0: passes

GCC 15.2.0: fails

GCC 16.1.0: fails

GCC trunk 17.0.0, build dated 2026-08-10: fails


Trigger and Workaround

Removing zvl256b makes the same source compile:

-march=rv64imafc_zve32f

The resulting scalable RVV binary successfully runs on VLEN=256 hardware, but
its code generation and performance differ because the compiler no longer
assumes a minimum 256-bit VLEN.