[Bug target/126803] GCC fails to process <riscv_vector.h> when targeting the valid zve32f_zvl256b ISA combination in C++.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126803

Zhongyao Chen <chenzhongyao.hit at gmail dot com> changed:

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                 CC|                            |chenzhongyao.hit at gmail dot com

--- Comment #1 from Zhongyao Chen <chenzhongyao.hit at gmail dot com> ---
I reproduced it.

The issue is that two different RVV ABI types are accidentally treated as the
same C++ type.

When `riscv_vector.h` processes `#pragma riscv intrinsic "vector"`, it first
has `vuint8m2_t` from the real `zve32f_zvl256b` target.  Later, the pragma
registers missing types with a wider temporary configuration and creates
`vuint8mf8_t`.

These are different RVV types, but both end up as vectors of 64 `uint8_t`
elements.  Since RISC-V was not comparing the `RVV type` attributes during C++
type comparison, GCC considered `vuint8m2_t` and `vuint8mf8_t` compatible.

That makes intrinsic declarations such as `vluxei8` look as if they have the
same parameter types, while their return types differ.  GCC then reports
"ambiguating new declaration".

To fix this, we can follow the ARM SVE approach and adds
`TARGET_COMP_TYPE_ATTRIBUTES` for RISC-V to compare `RVV type` and `RVV
sizeless type`.