[Bug target/124956] Improve conditional shift by 6 for leela on risc64

"law at gcc dot gnu.org via Gcc-bugs" <[email protected]>
Newsgroups gmane.comp.gcc.bugs
Message-ID <[email protected]/bugzilla/> 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124956
Bug 124956 depends on bug 125731, which changed state.

Bug 125731 Summary: Improve RISC-V sequence for conditional xor with a constant
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125731

           What    |Removed                     |Added
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             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED
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