[gcc r16-9242] Daily bump.

https://gcc.gnu.org/g:8387dc19bc818e1e717096cb99299edf850a5ab9

commit r16-9242-g8387dc19bc818e1e717096cb99299edf850a5ab9
Author: GCC Administrator <[email protected]>
Date:   Wed Jul 8 00:20:34 2026 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 82 +++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/testsuite/ChangeLog | 38 +++++++++++++++++++++++
 3 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fb2b171a0e9f..723c0d6ac0ee 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,85 @@
+2026-07-07  Stafford Horne  <[email protected]>
+
+	Backported from master:
+	2026-07-07  Stafford Horne  <[email protected]>
+
+	PR target/126081
+	* config/or1k/or1k.cc (or1k_hard_regno_mode_ok): Stop allowing
+	SImode for FLAG_REGS.
+	(or1k_can_change_mode_class): Stop allowing SImode for
+	FLAG_REGS.
+	(or1k_noce_conversion_profitable_p): Always check
+	or1k_is_cmov_insn.
+
+2026-07-07  Stafford Horne  <[email protected]>
+
+	Backported from master:
+	2026-06-14  Stafford Horne  <[email protected]>
+
+	* config/or1k/or1k.md (cbranchsi4): Add clobber clause.
+
+2026-07-07  Stafford Horne  <[email protected]>
+
+	Backported from master:
+	2026-06-14  Stafford Horne  <[email protected]>
+
+	* config/or1k/or1k.h (SHIFT_COUNT_TRUNCATED): Define.
+	* config/or1k/or1k.md (rotrsi3): Rename reg_or_u6_operand to
+	reg_or_u5_operand.
+	(<shift_op>si3): Ditto.
+	* config/or1k/predicates.md (reg_or_u6_operand): Remove.
+	(reg_or_u5_operand): New predicate.
+
+2026-07-07  Jeevitha  <[email protected]>
+
+	Backported from master:
+	2026-06-24  Jeevitha Palanisamy  <[email protected]>
+
+	* config/rs6000/altivec.md (V16QI_V2DI): New mode iterator.
+	(add<mode>3): Split into two patterns to support future ISA
+	alternatives.
+	(sub<mode>3): Likewise.
+	* config/rs6000/vsx.md (VIArith): New mode iterator.
+	(vsx_mul<mode>3): New insn pattern.
+	(smul<mode>3_highpart): Split into mode-specific patterns.
+	(umul<mode>3_highpart): Likewise.
+	(smulv8hi3_highpart): New insn pattern.
+	(smulv4si3_highpart): Likewise.
+	(smulv2di3_highpart): Likewise.
+	(umulv8hi3_highpart): Likewise.
+	(umulv4si3_highpart): Likewise.
+	(umulv2di3_highpart): Likewise.
+	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvmulhuh): New
+	builtin.
+	(__builtin_vsx_xvmulhsh): Likewise.
+	* config/rs6000/rs6000-overload.def (__builtin_vec_mulh): Add
+	overloads for vector multiply-high signed/unsigned halfword.
+	* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add entry for
+	BSTZ_FUTURE_VSX.
+	(stanza_map): Add future-vsx stanza mapping.
+	(enable_string): Add ENB_FUTURE_VSX.
+	(write_decls): Add ENB_FUTURE_VSX to the bif_enable enum in the
+	generated header file.
+	* config/rs6000/rs6000.md (define_attr "isa"): Add future to the list
+	of ISA values.
+	(define_attr "enabled"): Add check for future ISA.
+	* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Handle
+	ENB_FUTURE_VSX and issue a diagnostic requiring -mcpu=future and -mvsx.
+	(rs6000_builtin_is_supported): Return TARGET_FUTURE && TARGET_VSX
+	for ENB_FUTURE_VSX built-ins.
+	* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions Available
+	on Future ISA): Document new functions.
+
+2026-07-07  Icenowy Zheng  <[email protected]>
+
+	Backported from master:
+	2026-07-01  Icenowy Zheng  <[email protected]>
+
+	PR target/126049
+	* config/riscv/autovec.md: Change fmin/fmax reduction initial
+	value from inf/-inf to NaN for proper semantics of corresponding
+	C funtion.
+
 2026-07-06  vekumar  <[email protected]>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a4e14241298d..60ebd5a31783 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20260707
+20260708
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b1bc34adfa51..d9bbeb24d4f5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,41 @@
+2026-07-07  Stafford Horne  <[email protected]>
+
+	Backported from master:
+	2026-07-07  Stafford Horne  <[email protected]>
+
+	PR target/126081
+	* gcc.target/or1k/pr126081.c: New test.
+
+2026-07-07  Jeevitha  <[email protected]>
+
+	Backported from master:
+	2026-07-01  Jeevitha Palanisamy  <[email protected]>
+
+	* gcc.target/powerpc/vsx_arith_builtin-1.c: Remove inline asm
+	that forces operands into FPRs.
+	* gcc.target/powerpc/vsx_arith_builtin-2.c: Likewise.
+	* gcc.target/powerpc/vsx_arith_vect_1.c: Likewiswe.
+
+2026-07-07  Jeevitha  <[email protected]>
+
+	Backported from master:
+	2026-06-24  Jeevitha Palanisamy  <[email protected]>
+
+	* gcc.target/powerpc/vsx_arith_builtin-1.c: New test.
+	* gcc.target/powerpc/vsx_arith_builtin-2.c: Likewise.
+	* gcc.target/powerpc/vsx_arith_builtin-3.c: Likewise.
+	* gcc.target/powerpc/vsx_arith_builtin-4.c: Likewise.
+	* gcc.target/powerpc/vsx_arith_vect_1.c: Likewise.
+	* gcc.target/powerpc/vsx_arith_vect_2.c: Likewise.
+
+2026-07-07  Icenowy Zheng  <[email protected]>
+
+	Backported from master:
+	2026-07-01  Icenowy Zheng  <[email protected]>
+
+	PR target/126049
+	* gcc.target/riscv/rvv/autovec/pr126049.c: New.
+
 2026-07-06  Jason Merrill  <[email protected]>
 
 	Backported from master: