[gcc r17-2272] s390: Remove -m31 support
Stefan Schulze Frielinghaus via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <20260709073027.076544BA2E11__40430.3958801151$1783582233$gmane$org@sourceware.org> |
https://gcc.gnu.org/g:035f177a1eab310ca2f2a1996b7c000ff70514af commit r17-2272-g035f177a1eab310ca2f2a1996b7c000ff70514af Author: Stefan Schulze Frielinghaus <[email protected]> Date: Thu Jul 9 09:28:12 2026 +0200 s390: Remove -m31 support This patch removes -m31 support and as a consequence -mesa support. Using the respective command line options result in errors whereas -m64 and -mzarch are still accepted for the sake of backwards compatibility but do not have any additional effect anymore since those are the defaults and only options, now. Since a 64-bit GAS defaults to -m64, do not explicitly specify -m64 -mzarch anymore. ChangeLog: * configure: Regenerate. * configure.ac: Remove deprecation warning for -m31. contrib/ChangeLog: * compare-all-tests: Remove opts -m31 and so on. * config-list.mk: Remove s390-linux-gnu. gcc/ChangeLog: * config.gcc: Remove target s390-*. Don't accept --with-mode=esa anymore. * config.host: Remove target s390-*. * config/host-linux.cc (TRY_EMPTY_VM_SPACE): Remove definition for s390. * config/s390/2827.md: Remove scheduling information for mnemonics which are only used by -m31 but not by -m64. * config/s390/2964.md: Ditto. * config/s390/3906.md: Ditto. * config/s390/3931.md: Ditto. * config/s390/8561.md: Ditto. * config/s390/9175.md: Ditto. * config/s390/constraints.md (ZL): Remove TARGET_64BIT test. * config/s390/driver-native.cc (s390_host_detect_local_cpu): Remove handling for -mesa/-mzarch. * config/s390/htmxlintrin.h (__TM_failure_address): Remove -m31 part. * config/s390/linux.h: Remove -m31 parts. * config/s390/predicates.md: Ditto. * config/s390/s390-builtins.def: Rename RTL expander name for s390_vsce[fg]. * config/s390/s390-c.cc (s390_cpu_cpp_builtins): Remove TARGET_{64BIT,ZARCH} tests. * config/s390/s390-d.cc (s390_d_target_versions): Remove TARGET_64BIT test. * config/s390/s390.cc: Remove -m31 parts. In particular, there is no need to distinguish between 64-bit registers in ABI contexts anymore which is why UNITS_PER_WORD and UNITS_PER_LONG always equal, now. Hence, replace UNITS_PER_LONG by UNITS_PER_WORD. * config/s390/s390.h: Ditto. * config/s390/s390.md: Ditto. Mode iterator GPR is replaced by DSI. Likewise, DGPR by new mode iterator TDSI. Remove mode iterators P, DW, W because they are singletons, now. * config/s390/s390.opt: Keep -m64 and -mzarch for backwards compatibility. Mark -m31 and -mesa as undocumented. * config/s390/s390.opt.urls: Regenerate. * config/s390/t-linux64: Remove -m31 parts. * config/s390/tpf.h (POINTERS_EXTEND_UNSIGNED): This is only required for TPF which is why it is moved from s390.h here. (TARGET_DEFAULT): Remove MASK_64BIT and MASK_ZARCH. * config/s390/vector.md: Remove -m31 parts. * config/s390/vx-builtins.md (vec_scatter_element<V_HW_2:mode>_SI): There is no need for multiplexing different address sizes for vec_scatter_element anymore. (vec_scatter_element<V_HW_32_64:mode>): Ditto. * configure: Regenerate. * configure.ac: Remove target s390-*. * doc/install.texi: Remove mentions of s390 without also referring to s390x. * doc/invoke.texi: Remove options -m31 and -mesa. Document that -m64 and -mzarch are the defaults, now, and that they don't have any additional effect when explicitly specified. * config/s390/s390x.h: Removed. libgcc/ChangeLog: * config.host: Remove target s390-*. Remove -m31 part. * config/s390/libgcc-glibc.ver: Remove -m31 part. * config/s390/morestack.S: Ditto. * config/s390/sfp-machine.h: Ditto. * configure: Regenerate. * configure.ac: Remove target s390-*. * generic-morestack.c: Remove -m31 part. * config/s390/32/_fixdfdi.c: Removed. * config/s390/32/_fixsfdi.c: Removed. * config/s390/32/_fixtfdi.c: Removed. * config/s390/32/_fixunsdfdi.c: Removed. * config/s390/32/_fixunssfdi.c: Removed. * config/s390/32/_fixunstfdi.c: Removed. * config/s390/32/t-floattodi: Removed. libgm2/ChangeLog: * configure.host: Remove s390 host part; keep s390x. libitm/ChangeLog: * config/s390/sjlj.S: Remove -m31 part. libstdc++-v3/ChangeLog: * configure.host: Remove s390 host part; keep s390x. gcc/testsuite/ChangeLog: * gcc.dg/asm-hard-reg-error-3.c: Remove target s390-*. * gcc.dg/builtin-bswap-8.c: Remove target s390-*. * gcc.dg/ifcvt-4.c: Remove -m31 part. * gcc.dg/optimize-bswaphi-1.c: Ditto. * gcc.dg/optimize-bswapsi-3.c: Ditto. * gcc.dg/optimize-bswapsi-4.c: Ditto. * gcc.dg/optimize-bswapsi-5.c: Ditto. * gcc.dg/optimize-bswapsi-6.c: Ditto. * gcc.dg/optimize-bswapsi-7.c: Ditto. * gcc.dg/pr120525.c: Ditto. * gcc.dg/tree-ssa/loop-1.c: Ditto. * gcc.misc-tests/linkage.exp: Ditto. * gcc.target/s390/addsub-signed-overflow-1.c: Ditto. * gcc.target/s390/addsub-signed-overflow-2.c: Ditto. * gcc.target/s390/asm-constant-1.c: Ditto. * gcc.target/s390/call-z10-pic-nodatarel.c: Ditto. * gcc.target/s390/call-z10-pic.c: Ditto. * gcc.target/s390/call-z10.c: Ditto. * gcc.target/s390/call-z9-pic-nodatarel.c: Ditto. * gcc.target/s390/call-z9-pic.c: Ditto. * gcc.target/s390/call-z9.c: Ditto. * gcc.target/s390/fcall-saved.c: Ditto. * gcc.target/s390/global-array-element-pic2.c: Ditto. * gcc.target/s390/insv-1.c: Ditto. * gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c: Ditto. * gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c: Ditto. * gcc.target/s390/larl-1.c: Ditto. * gcc.target/s390/leaf-profile.c: Ditto. * gcc.target/s390/load-relative-check.c: Ditto. * gcc.target/s390/load-thread-pointer-once-2.c: Ditto. * gcc.target/s390/load-thread-pointer-once.c: Ditto. * gcc.target/s390/loc-1.c: Ditto. * gcc.target/s390/md/andc-splitter-2.c: Ditto. * gcc.target/s390/mrecord-mcount.c: Ditto. * gcc.target/s390/mul-signed-overflow-1.c: Ditto. * gcc.target/s390/mul-signed-overflow-2.c: Ditto. * gcc.target/s390/not.c: Ditto. * gcc.target/s390/pr42224.c: Guard as a TPF test. * gcc.target/s390/preserve-args-1.c: Remove -m31 part. * gcc.target/s390/preserve-args-3.c: Ditto. * gcc.target/s390/risbg-ll-1.c: Ditto. * gcc.target/s390/risbg-ll-2.c: Ditto. * gcc.target/s390/risbg-ll-3.c: Ditto. * gcc.target/s390/stack-protector-guard-tls-1.c: Ditto. * gcc.target/s390/target-attribute/tattr-12.c: Ditto. * gcc.target/s390/target-attribute/tattr-15.c: Ditto. * gcc.target/s390/tls.c: Ditto. * gcc.target/s390/uaddc-1.c: Ditto. * gcc.target/s390/uaddc-2.c: Ditto. * gcc.target/s390/uaddc-3.c: Ditto. * gcc.target/s390/usubc-1.c: Ditto. * gcc.target/s390/usubc-2.c: Ditto. * gcc.target/s390/usubc-3.c: Ditto. * gcc.target/s390/vector/pattern-avg-1.c: Ditto. * gcc.target/s390/vector/vec-abi-1.c: Ditto. * gcc.target/s390/vector/vec-abi-3.c: Ditto. * gcc.target/s390/vector/vec-abi-4.c: Ditto. * gcc.target/s390/vector/vec-abi-vararg-1.c: Ditto. * gcc.target/s390/vector/vec-scalar-cmp-1.c: Ditto. * gcc.target/s390/zero-scratch-regs-1.c: Ditto. * gcc.target/s390/zvector/vec-cmp-1.c: Ditto. * gcc.target/s390/20020926-1.c: Removed. * gcc.target/s390/20140327-1.c: Removed. * gcc.target/s390/dwarfregtable-1.c: Removed. * gcc.target/s390/dwarfregtable-2.c: Removed. * gcc.target/s390/fp2int1.c: Removed. * gcc.target/s390/mnop-mcount-m31-mzarch.c: Removed. * gcc.target/s390/pr102222.c: Removed. * gcc.target/s390/pr106355-2.c: Removed. * gcc.target/s390/pr106355-3.c: Removed. * gcc.target/s390/pr119873-5.c: Removed. * gcc.target/s390/pr61078.c: Removed. * gcc.target/s390/stack-clash-4.c: Removed. * gcc.target/s390/stack-clash-5.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-1.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-10.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-11.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-12.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-13.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-14.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-15.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-16.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-17.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-18.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-19.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-2.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-20.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-21.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-22.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-23.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-24.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-25.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-26.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-27.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-28.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-29.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-3.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-30.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-31.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-32.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-4.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-5.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-6.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-7.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-8.c: Removed. * gcc.target/s390/target-attribute/tattr-m31-9.c: Removed. Diff: --- configure | 16 - configure.ac | 15 - contrib/compare-all-tests | 1 - contrib/config-list.mk | 2 +- gcc/config.gcc | 33 +- gcc/config.host | 4 +- gcc/config/host-linux.cc | 2 - gcc/config/s390/2827.md | 56 +- gcc/config/s390/2964.md | 42 +- gcc/config/s390/3906.md | 40 +- gcc/config/s390/3931.md | 50 +- gcc/config/s390/8561.md | 38 +- gcc/config/s390/9175.md | 44 +- gcc/config/s390/constraints.md | 4 +- gcc/config/s390/driver-native.cc | 16 +- gcc/config/s390/htmxlintrin.h | 4 - gcc/config/s390/linux.h | 29 +- gcc/config/s390/predicates.md | 16 +- gcc/config/s390/s390-builtins.def | 4 +- gcc/config/s390/s390-c.cc | 6 +- gcc/config/s390/s390-d.cc | 9 +- gcc/config/s390/s390.cc | 1026 ++----- gcc/config/s390/s390.h | 196 +- gcc/config/s390/s390.md | 2865 ++++++-------------- gcc/config/s390/s390.opt | 15 +- gcc/config/s390/s390.opt.urls | 6 - gcc/config/s390/s390x.h | 27 - gcc/config/s390/t-linux64 | 12 +- gcc/config/s390/tpf.h | 7 +- gcc/config/s390/vector.md | 28 +- gcc/config/s390/vx-builtins.md | 48 +- gcc/configure | 25 +- gcc/configure.ac | 25 +- gcc/doc/install.texi | 6 +- gcc/doc/invoke.texi | 30 +- gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c | 5 +- gcc/testsuite/gcc.dg/builtin-bswap-8.c | 1 - gcc/testsuite/gcc.dg/ifcvt-4.c | 1 - gcc/testsuite/gcc.dg/optimize-bswaphi-1.c | 1 - gcc/testsuite/gcc.dg/optimize-bswapsi-3.c | 1 - gcc/testsuite/gcc.dg/optimize-bswapsi-4.c | 1 - gcc/testsuite/gcc.dg/optimize-bswapsi-5.c | 1 - gcc/testsuite/gcc.dg/optimize-bswapsi-6.c | 1 - gcc/testsuite/gcc.dg/optimize-bswapsi-7.c | 1 - gcc/testsuite/gcc.dg/pr120525.c | 1 - gcc/testsuite/gcc.dg/tree-ssa/loop-1.c | 5 - gcc/testsuite/gcc.misc-tests/linkage.exp | 9 - gcc/testsuite/gcc.target/s390/20020926-1.c | 14 - gcc/testsuite/gcc.target/s390/20140327-1.c | 10 - .../gcc.target/s390/addsub-signed-overflow-1.c | 9 +- .../gcc.target/s390/addsub-signed-overflow-2.c | 9 +- gcc/testsuite/gcc.target/s390/asm-constant-1.c | 13 +- .../gcc.target/s390/call-z10-pic-nodatarel.c | 11 +- gcc/testsuite/gcc.target/s390/call-z10-pic.c | 9 +- gcc/testsuite/gcc.target/s390/call-z10.c | 5 +- .../gcc.target/s390/call-z9-pic-nodatarel.c | 3 +- gcc/testsuite/gcc.target/s390/call-z9-pic.c | 3 +- gcc/testsuite/gcc.target/s390/call-z9.c | 3 +- gcc/testsuite/gcc.target/s390/dwarfregtable-1.c | 21 - gcc/testsuite/gcc.target/s390/dwarfregtable-2.c | 21 - gcc/testsuite/gcc.target/s390/fcall-saved.c | 8 +- gcc/testsuite/gcc.target/s390/fp2int1.c | 95 - .../gcc.target/s390/global-array-element-pic2.c | 5 +- gcc/testsuite/gcc.target/s390/insv-1.c | 8 +- .../s390/isfinite-isinf-isnormal-signbit-2.c | 6 +- .../s390/isfinite-isinf-isnormal-signbit-3.c | 6 +- gcc/testsuite/gcc.target/s390/larl-1.c | 5 +- gcc/testsuite/gcc.target/s390/leaf-profile.c | 1 - .../gcc.target/s390/load-relative-check.c | 12 +- .../gcc.target/s390/load-thread-pointer-once-2.c | 3 +- .../gcc.target/s390/load-thread-pointer-once.c | 3 +- gcc/testsuite/gcc.target/s390/loc-1.c | 6 +- gcc/testsuite/gcc.target/s390/md/andc-splitter-2.c | 8 +- .../gcc.target/s390/mnop-mcount-m31-mzarch.c | 8 - gcc/testsuite/gcc.target/s390/mrecord-mcount.c | 3 +- .../gcc.target/s390/mul-signed-overflow-1.c | 7 +- .../gcc.target/s390/mul-signed-overflow-2.c | 5 +- gcc/testsuite/gcc.target/s390/not.c | 3 +- gcc/testsuite/gcc.target/s390/pr102222.c | 16 - gcc/testsuite/gcc.target/s390/pr106355-2.c | 8 - gcc/testsuite/gcc.target/s390/pr106355-3.c | 8 - gcc/testsuite/gcc.target/s390/pr119873-5.c | 11 - gcc/testsuite/gcc.target/s390/pr42224.c | 3 + gcc/testsuite/gcc.target/s390/pr61078.c | 26 - gcc/testsuite/gcc.target/s390/preserve-args-1.c | 3 +- gcc/testsuite/gcc.target/s390/preserve-args-3.c | 3 +- gcc/testsuite/gcc.target/s390/risbg-ll-1.c | 96 +- gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 18 +- gcc/testsuite/gcc.target/s390/risbg-ll-3.c | 11 +- gcc/testsuite/gcc.target/s390/stack-clash-4.c | 10 - gcc/testsuite/gcc.target/s390/stack-clash-5.c | 10 - .../gcc.target/s390/stack-protector-guard-tls-1.c | 11 +- .../gcc.target/s390/target-attribute/tattr-12.c | 15 +- .../gcc.target/s390/target-attribute/tattr-15.c | 6 +- .../gcc.target/s390/target-attribute/tattr-m31-1.c | 353 --- .../s390/target-attribute/tattr-m31-10.c | 353 --- .../s390/target-attribute/tattr-m31-11.c | 353 --- .../s390/target-attribute/tattr-m31-12.c | 353 --- .../s390/target-attribute/tattr-m31-13.c | 353 --- .../s390/target-attribute/tattr-m31-14.c | 353 --- .../s390/target-attribute/tattr-m31-15.c | 353 --- .../s390/target-attribute/tattr-m31-16.c | 353 --- .../s390/target-attribute/tattr-m31-17.c | 353 --- .../s390/target-attribute/tattr-m31-18.c | 353 --- .../s390/target-attribute/tattr-m31-19.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-2.c | 353 --- .../s390/target-attribute/tattr-m31-20.c | 353 --- .../s390/target-attribute/tattr-m31-21.c | 353 --- .../s390/target-attribute/tattr-m31-22.c | 353 --- .../s390/target-attribute/tattr-m31-23.c | 353 --- .../s390/target-attribute/tattr-m31-24.c | 353 --- .../s390/target-attribute/tattr-m31-25.c | 353 --- .../s390/target-attribute/tattr-m31-26.c | 353 --- .../s390/target-attribute/tattr-m31-27.c | 353 --- .../s390/target-attribute/tattr-m31-28.c | 353 --- .../s390/target-attribute/tattr-m31-29.c | 177 -- .../gcc.target/s390/target-attribute/tattr-m31-3.c | 353 --- .../s390/target-attribute/tattr-m31-30.c | 177 -- .../s390/target-attribute/tattr-m31-31.c | 353 --- .../s390/target-attribute/tattr-m31-32.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-4.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-5.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-6.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-7.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-8.c | 353 --- .../gcc.target/s390/target-attribute/tattr-m31-9.c | 353 --- gcc/testsuite/gcc.target/s390/tls.c | 3 +- gcc/testsuite/gcc.target/s390/uaddc-1.c | 7 +- gcc/testsuite/gcc.target/s390/uaddc-2.c | 5 +- gcc/testsuite/gcc.target/s390/uaddc-3.c | 6 +- gcc/testsuite/gcc.target/s390/usubc-1.c | 7 +- gcc/testsuite/gcc.target/s390/usubc-2.c | 5 +- gcc/testsuite/gcc.target/s390/usubc-3.c | 9 +- .../gcc.target/s390/vector/pattern-avg-1.c | 3 +- gcc/testsuite/gcc.target/s390/vector/vec-abi-1.c | 7 +- gcc/testsuite/gcc.target/s390/vector/vec-abi-3.c | 8 +- gcc/testsuite/gcc.target/s390/vector/vec-abi-4.c | 6 +- .../gcc.target/s390/vector/vec-abi-vararg-1.c | 17 +- .../gcc.target/s390/vector/vec-scalar-cmp-1.c | 20 +- .../gcc.target/s390/zero-scratch-regs-1.c | 15 +- gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c | 72 +- libgcc/config.host | 14 +- libgcc/config/s390/32/_fixdfdi.c | 113 - libgcc/config/s390/32/_fixsfdi.c | 107 - libgcc/config/s390/32/_fixtfdi.c | 122 - libgcc/config/s390/32/_fixunsdfdi.c | 120 - libgcc/config/s390/32/_fixunssfdi.c | 114 - libgcc/config/s390/32/_fixunstfdi.c | 125 - libgcc/config/s390/32/t-floattodi | 5 - libgcc/config/s390/libgcc-glibc.ver | 43 - libgcc/config/s390/morestack.S | 241 -- libgcc/config/s390/sfp-machine.h | 4 - libgcc/configure | 2 +- libgcc/configure.ac | 2 +- libgcc/generic-morestack.c | 2 - libgm2/configure.host | 3 - libitm/config/s390/sjlj.S | 24 - libstdc++-v3/configure.host | 3 - 158 files changed, 1562 insertions(+), 15969 deletions(-) diff --git a/configure b/configure index f5673e863419..79c324786e7a 100755 --- a/configure +++ b/configure @@ -11752,22 +11752,6 @@ case "$target:$have_compiler:$host:$target:$enable_multilib" in ;; esac -# For s390, -m31 is deprecated. Emit a warning if --enable-multilib and -# --enable-obsolete are explicitly specified. If --enable-multilib is -# specified implicitly or --enable-obsolete is missing, error out. -case "$target:$enable_multilib:$enable_obsolete" in - s390*:yes:yes) - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Support for -m31 is deprecated and will be removed." >&5 -$as_echo "$as_me: WARNING: Support for -m31 is deprecated and will be removed." >&2;} - ;; - s390*::*) - as_fn_error $? "Support for -m31 is deprecated and will be removed. Explicitly specify --disable-multilib or --enable-multilib --enable-obsolete to build it anyway." "$LINENO" 5 - ;; - s390*:yes:*) - as_fn_error $? "Support for -m31 is deprecated and will be removed. Specify --enable-obsolete to build it anyway." "$LINENO" 5 - ;; -esac - # Default to --enable-multilib. if test x${enable_multilib} = x ; then target_configargs="--enable-multilib ${target_configargs}" diff --git a/configure.ac b/configure.ac index c953a5823c0a..60887fb7fe00 100644 --- a/configure.ac +++ b/configure.ac @@ -3826,21 +3826,6 @@ case "$target:$have_compiler:$host:$target:$enable_multilib" in ;; esac -# For s390, -m31 is deprecated. Emit a warning if --enable-multilib and -# --enable-obsolete are explicitly specified. If --enable-multilib is -# specified implicitly or --enable-obsolete is missing, error out. -case "$target:$enable_multilib:$enable_obsolete" in - s390*:yes:yes) - AC_MSG_WARN([Support for -m31 is deprecated and will be removed.]) - ;; - s390*::*) - AC_MSG_ERROR([Support for -m31 is deprecated and will be removed. Explicitly specify --disable-multilib or --enable-multilib --enable-obsolete to build it anyway.]) - ;; - s390*:yes:*) - AC_MSG_ERROR([Support for -m31 is deprecated and will be removed. Specify --enable-obsolete to build it anyway.]) - ;; -esac - # Default to --enable-multilib. if test x${enable_multilib} = x ; then target_configargs="--enable-multilib ${target_configargs}" diff --git a/contrib/compare-all-tests b/contrib/compare-all-tests index 561b2195c64a..3280787ebb1e 100644 --- a/contrib/compare-all-tests +++ b/contrib/compare-all-tests @@ -29,7 +29,6 @@ mips_opts='-msoft-float/-mgp32/-mips16 -mabi=32/-mfp32/-mgp32/-mips16 -mabi=o64/ mn10300_opts='-mam33 -mam33-2' pa_opts='-march=2.0 -march=1.0 -march=1.1' ppc_opts='-m32 -m64' -s390_opts='-m31 -m31/-mzarch -m64' sh_opts='-m3 -m3e -m4 -m4a -m4al -m4/-mieee -m1 -m1/-mno-cbranchdi -m2a -m2a/-mieee -m2e -m2e/-mieee' sparc_opts='-mcpu=v8/-m32 -mcpu=v9/-m32 -m64' diff --git a/contrib/config-list.mk b/contrib/config-list.mk index 69f5aed476d3..c7f01da3bd2d 100644 --- a/contrib/config-list.mk +++ b/contrib/config-list.mk @@ -94,7 +94,7 @@ LIST = \ pru-elf \ riscv32-unknown-linux-gnu riscv64-unknown-linux-gnu \ powerpc-ibm-aix7.1 powerpc-ibm-aix7.2 \ - rl78-elf rx-elf s390-linux-gnu s390x-linux-gnu s390x-ibm-tpf sh-elf \ + rl78-elf rx-elf s390x-linux-gnu s390x-ibm-tpf sh-elf \ shle-linux sh-netbsdelf sh-superh-elf \ sh-rtems sh-wrs-vxworks sparc-elf \ sparc-leon-elf sparc-rtems sparc-linux-gnu \ diff --git a/gcc/config.gcc b/gcc/config.gcc index 15f663cfb642..0477bf22c8a0 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -276,15 +276,6 @@ case ${target} in fi;; esac -case ${target} in - s390-*) - if test "x$enable_obsolete" != xyes; then - echo "*** Configuration ${target} is deprecated and will be removed." >&2 - echo "*** Specify --enable-obsolete to build it anyway." >&2 - exit 1 - fi;; -esac - # Unsupported targets list. Do not put an entry in this list unless # it would otherwise be caught by a more permissive pattern. The list # should be in alphabetical order. @@ -310,6 +301,7 @@ case ${target}${target_min} in | pdp11-*-bsd \ | powerpc*-*-linux*paired* \ | powerpc*-*-*spe* \ + | s390-*-* \ | sparc-hal-solaris2* \ | spu*-*-* \ | thumb-*-* \ @@ -603,7 +595,7 @@ sparc*-*-*) d_target_objs="sparc-d.o" extra_headers="visintrin.h" ;; -s390*-*-*) +s390x-*-*) cpu_type=s390 d_target_objs="s390-d.o" extra_options="${extra_options} fused-madd.opt" @@ -3270,17 +3262,8 @@ rx-*-linux*) tm_file="elfos.h linux.h glibc-stdint.h rx/linux.h ../../libgcc/config/rx/rx-abi.h" tmake_file="${tmake_file} rx/t-linux" ;; -s390-*-linux*) - tm_file="s390/s390.h elfos.h gnu-user.h linux.h glibc-stdint.h s390/linux.h" - c_target_objs="${c_target_objs} s390-c.o" - cxx_target_objs="${cxx_target_objs} s390-c.o" - if test x$enable_targets = xall; then - tmake_file="${tmake_file} s390/t-linux64" - fi - tmake_file="${tmake_file} s390/t-s390" - ;; s390x-*-linux*) - tm_file="s390/s390x.h s390/s390.h elfos.h gnu-user.h linux.h glibc-stdint.h s390/linux.h" + tm_file="s390/s390.h elfos.h gnu-user.h linux.h glibc-stdint.h s390/linux.h" tm_p_file="linux-protos.h s390/s390-protos.h" c_target_objs="${c_target_objs} s390-c.o" cxx_target_objs="${cxx_target_objs} s390-c.o" @@ -3290,7 +3273,7 @@ s390x-*-linux*) tmake_file="${tmake_file} s390/t-linux64 s390/t-s390" ;; s390x-ibm-tpf*) - tm_file="s390/s390x.h s390/s390.h elfos.h glibc-stdint.h s390/tpf.h" + tm_file="s390/s390.h elfos.h glibc-stdint.h s390/tpf.h" tm_p_file=s390/s390-protos.h c_target_objs="${c_target_objs} s390-c.o" cxx_target_objs="${cxx_target_objs} s390-c.o" @@ -5883,7 +5866,7 @@ case "${target}" in fi ;; - s390*-*-*) + s390x-*-*) supported_defaults="arch mode tune" for which in arch tune; do @@ -5900,9 +5883,13 @@ case "${target}" in done case ${with_mode} in - "" | esa | zarch) + "" | zarch) # OK ;; + esa) + echo "ESA/390 mode is no longer supported." 1>&2 + exit 1 + ;; *) echo "Unknown architecture mode used in --with-mode=$with_mode." 1>&2 exit 1 diff --git a/gcc/config.host b/gcc/config.host index 8b809a8d5ddc..c9be68acb82f 100644 --- a/gcc/config.host +++ b/gcc/config.host @@ -173,9 +173,9 @@ case ${host} in ;; esac ;; - s390-*-* | s390x-*-*) + s390x-*-*) case ${target} in - s390-*-* | s390x-*-*) + s390x-*-*) host_extra_gcc_objs="driver-native.o" host_xmake_file="${host_xmake_file} s390/x-native" ;; diff --git a/gcc/config/host-linux.cc b/gcc/config/host-linux.cc index e3ccc06eb810..57b9b46ccc33 100644 --- a/gcc/config/host-linux.cc +++ b/gcc/config/host-linux.cc @@ -78,8 +78,6 @@ # define TRY_EMPTY_VM_SPACE 0x60000000 #elif defined(__s390x__) # define TRY_EMPTY_VM_SPACE 0x8000000000 -#elif defined(__s390__) -# define TRY_EMPTY_VM_SPACE 0x60000000 #elif defined(__sparc__) && defined(__LP64__) # define TRY_EMPTY_VM_SPACE 0x8000000000 #elif defined(__sparc__) diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md index 6aa5f76eca87..d043ebd86004 100644 --- a/gcc/config/s390/2827.md +++ b/gcc/config/s390/2827.md @@ -19,11 +19,11 @@ ;; <http://www.gnu.org/licenses/>. (define_attr "zEC12_cracked" "" - (cond [(eq_attr "mnemonic" "cgdbr,clfxtr,cdgtr,celfbr,cxgtr,clfebr,clc,lngfr,cs,cfxbr,xc,clfdbr,basr,ex,cxlgtr,clfdtr,srdl,lpgfr,cdlgbr,cgxtr,cxlftr,nc,cxftr,cdfbr,clfxbr,cdftr,clgxbr,cgdtr,cxlgbr,mvc,clgdtr,cegbr,cfebr,cdlftr,sldl,cdlgtr,csg,chhsi,clgebr,cxgbr,cxfbr,cdlfbr,cgebr,lzxr,oc,cdgbr,brasl,cgxbr,cxlfbr,clgxtr,exrl,cfdbr,celgbr,clgdbr,lxr,cpsdr,lcgfr,bras,srda,cefbr") (const_int 1)] + (cond [(eq_attr "mnemonic" "cgdbr,clfxtr,cdgtr,celfbr,cxgtr,clfebr,clc,lngfr,cs,cfxbr,xc,clfdbr,basr,ex,cxlgtr,clfdtr,lpgfr,cdlgbr,cgxtr,cxlftr,nc,cxftr,cdfbr,clfxbr,cdftr,clgxbr,cgdtr,cxlgbr,mvc,clgdtr,cegbr,cfebr,cdlftr,cdlgtr,csg,chhsi,clgebr,cxgbr,cxfbr,cdlfbr,cgebr,lzxr,oc,cdgbr,brasl,cgxbr,cxlfbr,clgxtr,exrl,cfdbr,celgbr,clgdbr,lxr,cpsdr,lcgfr,bras,cefbr") (const_int 1)] (const_int 0))) (define_attr "zEC12_expanded" "" - (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr,dsg,cds,dr,stm,mvc,dl,cdsg,stmy,dlg,stmg,lam") (const_int 1)] + (cond [(eq_attr "mnemonic" "dsgr,dsgf,stam,dsgfr,dlgr,dsg,mvc,cdsg,dlg,stmg,lam") (const_int 1)] (const_int 0))) (define_attr "zEC12_endgroup" "" @@ -31,12 +31,12 @@ (const_int 0))) (define_attr "zEC12_groupalone" "" - (cond [(eq_attr "mnemonic" "lnxbr,madb,ltxtr,clc,axtr,msebr,slbgr,xc,alcr,lpxbr,slbr,maebr,mlg,mfy,lxdtr,maeb,lxeb,nc,mxtr,sxtr,dxbr,alc,msdbr,ltxbr,lxdb,madbr,lxdbr,lxebr,mvc,m,mseb,mlr,mlgr,slb,tcxb,msdb,sqxbr,alcgr,oc,flogr,alcg,mxbr,dxtr,axbr,mr,sxbr,slbg,ml,lcxbr,bcr_flush") (const_int 1)] + (cond [(eq_attr "mnemonic" "lnxbr,madb,ltxtr,clc,axtr,msebr,slbgr,xc,alcr,lpxbr,slbr,maebr,mlg,lxdtr,maeb,lxeb,nc,mxtr,sxtr,dxbr,alc,msdbr,ltxbr,lxdb,madbr,lxdbr,lxebr,mvc,mseb,mlgr,slb,tcxb,msdb,sqxbr,alcgr,oc,flogr,alcg,mxbr,dxtr,axbr,sxbr,slbg,lcxbr,bcr_flush") (const_int 1)] (const_int 0))) (define_insn_reservation "zEC12_simple_int" 0 (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "ltg,ogrk,lr,lghrl,x,asi,lhr,ar,lhrl,llgfr,clghrl,cgr,cli,agrk,ic,lrv,clg,cy,cghi,sy,clgfr,al,tm,lang,lghr,laa,ark,lh,or,icy,xi,n,llihl,afi,cs,nrk,sth,lgr,l,lcr,stey,xg,crt,slgfr,ny,ld,j,llihh,slgr,clfhsi,slg,lb,lgrl,lrl,llihf,llcr,laxg,mvghi,rllg,xrk,laag,alhsik,algfi,algr,aly,agfi,lrvr,d,crl,llgc,tmhl,algsi,lgh,icmh,clhrl,xgrk,icm,iilf,ork,cg,ldgr,lgf,iihf,llghr,sg,stam,tmhh,slgf,basr,lgb,cgfi,lax,clfit,lrvgr,nihl,ni,srdl,srk,xihf,stgrl,sthrl,algf,cgit,ng,lat,llghrl,ltgr,nihh,clgfrl,srlk,agr,ler,bcr_flush,stcy,cds,clfi,nihf,ly,clt,lgat,alg,lhy,lgfrl,clghsi,clrt,tmll,srlg,ay,sty,clr,lgfi,lan,clgt,ahik,sra,algrk,clgr,tmy,tmlh,alghsik,lcgr,mvi,ltgf,xr,larl,ldr,llgcr,clgrt,clrl,cghsi,cliy,oy,ogr,llgt,slr,chi,s,icmy,llc,ngr,clhhsi,ltgfr,llill,lhi,o,sll,clgrl,clgf,m viy,algfr,rll,sldl,lg,niy,st,sgr,ag,le,xgr,cr,stg,llilh,sr,cdsg,sllk,stoc,csg,clgit,chhsi,strl,llilf,lndfr,ngrk,clgfi,llgh,oill,la,llhrl,stc,lghi,oihl,xiy,sllg,llgf,cgrt,cl,sl,oi,oilh,nr,srak,oihh,e ar,slgrk,og,c,slgfi,sthy,oilf,oiy,oihf,a,cfi,srag,brasl,alr,cgrl,llgfrl,cit,ley,exrl,lcdfr,lay,xilf,alsi,mvhhi,srl,chsi,lgfr,lrvg,cly,sgrk,ahi,nill,jg,slrk,lxr,sar,slfi,cpsdr,lcgfr,aghik,nilh,mvhi,lpdfr,xy,alrk,lao,agsi,ldy,nilf,llhr,alfi,laog,sly,aghi,bras,srda,lt,lbr,lzxr,lzdr,lzer")) "nothing") + (eq_attr "mnemonic" "ltg,ogrk,lr,lghrl,x,asi,lhr,ar,lhrl,llgfr,clghrl,cgr,cli,agrk,ic,lrv,clg,cy,cghi,sy,clgfr,al,tm,lang,lghr,laa,ark,lh,or,icy,xi,n,llihl,afi,cs,nrk,sth,lgr,l,lcr,stey,xg,crt,slgfr,ny,ld,j,llihh,slgr,clfhsi,slg,lb,lgrl,lrl,llihf,llcr,laxg,mvghi,rllg,xrk,laag,alhsik,algfi,algr,aly,agfi,lrvr,crl,llgc,tmhl,algsi,lgh,icmh,clhrl,xgrk,icm,iilf,ork,cg,ldgr,lgf,iihf,llghr,sg,stam,tmhh,slgf,basr,lgb,cgfi,lax,clfit,lrvgr,nihl,ni,srk,xihf,stgrl,sthrl,algf,cgit,ng,lat,llghrl,ltgr,nihh,clgfrl,srlk,agr,ler,bcr_flush,stcy,clfi,nihf,ly,clt,lgat,alg,lhy,lgfrl,clghsi,clrt,tmll,srlg,ay,sty,clr,lgfi,lan,clgt,ahik,sra,algrk,clgr,tmy,tmlh,alghsik,lcgr,mvi,ltgf,xr,larl,ldr,llgcr,clgrt,clrl,cghsi,cliy,oy,ogr,llgt,slr,chi,s,icmy,llc,ngr,clhhsi,ltgfr,llill,lhi,o,sll,clgrl,clgf,mviy,algfr,r ll,lg,niy,st,sgr,ag,le,xgr,cr,stg,llilh,sr,cdsg,sllk,stoc,csg,clgit,chhsi,strl,llilf,lndfr,ngrk,clgfi,llgh,oill,la,llhrl,stc,lghi,oihl,xiy,sllg,llgf,cgrt,cl,sl,oi,oilh,nr,srak,oihh,ear,slgrk,og,c,sl gfi,sthy,oilf,oiy,oihf,a,cfi,srag,brasl,alr,cgrl,llgfrl,cit,ley,exrl,lcdfr,lay,xilf,alsi,mvhhi,srl,chsi,lgfr,lrvg,cly,sgrk,ahi,nill,jg,slrk,lxr,sar,slfi,cpsdr,lcgfr,aghik,nilh,mvhi,lpdfr,xy,alrk,lao,agsi,ldy,nilf,llhr,alfi,laog,sly,aghi,bras,lt,lbr,lzxr,lzdr,lzer")) "nothing") (define_insn_reservation "zEC12_simple_fp" 0 (and (eq_attr "cpu" "zEC12") @@ -74,10 +74,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "mhy")) "nothing") -(define_insn_reservation "zEC12_dlr" 25 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "dlr")) "nothing") - (define_insn_reservation "zEC12_ltxtr" 18 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ltxtr")) "nothing") @@ -142,10 +138,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cgf")) "nothing") -(define_insn_reservation "zEC12_lmy" 0 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "lmy")) "nothing") - (define_insn_reservation "zEC12_std" 3 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "std")) "nothing") @@ -222,10 +214,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ex")) "nothing") -(define_insn_reservation "zEC12_mfy" 7 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "mfy")) "nothing") - (define_insn_reservation "zEC12_cxlgtr" 4 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cxlgtr")) "nothing") @@ -338,10 +326,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ltxbr")) "nothing") -(define_insn_reservation "zEC12_dr" 16 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "dr")) "nothing") - (define_insn_reservation "zEC12_lxdb" 3 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "lxdb")) "nothing") @@ -362,10 +346,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "agf")) "nothing") -(define_insn_reservation "zEC12_lm" 0 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "lm")) "nothing") - (define_insn_reservation "zEC12_msgfr" 6 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "msgfr")) "nothing") @@ -374,10 +354,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "lxdbr")) "nothing") -(define_insn_reservation "zEC12_stm" 0 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "stm")) "nothing") - (define_insn_reservation "zEC12_cgdtr" 2 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cgdtr")) "nothing") @@ -398,10 +374,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "sqdbr")) "nothing") -(define_insn_reservation "zEC12_dl" 25 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "dl")) "nothing") - (define_insn_reservation "zEC12_cfebr" 2 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cfebr")) "nothing") @@ -414,10 +386,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "lnr")) "nothing") -(define_insn_reservation "zEC12_m" 7 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "m")) "nothing") - (define_insn_reservation "zEC12_ipm" 3 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ipm")) "nothing") @@ -434,10 +402,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ddbr")) "nothing") -(define_insn_reservation "zEC12_stmy" 0 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "stmy")) "nothing") - (define_insn_reservation "zEC12_ste" 4 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ste")) "nothing") @@ -446,10 +410,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ahy")) "nothing") -(define_insn_reservation "zEC12_mlr" 7 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "mlr")) "nothing") - (define_insn_reservation "zEC12_sqeb" 29 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "sqeb")) "nothing") @@ -562,10 +522,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "axbr")) "nothing") -(define_insn_reservation "zEC12_mr" 7 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "mr")) "nothing") - (define_insn_reservation "zEC12_stmg" 0 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "stmg")) "nothing") @@ -598,10 +554,6 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "slbg")) "nothing") -(define_insn_reservation "zEC12_ml" 7 - (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "ml")) "nothing") - (define_insn_reservation "zEC12_lam" 0 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "lam")) "nothing") diff --git a/gcc/config/s390/2964.md b/gcc/config/s390/2964.md index 6abdf2199755..91d58fd16b55 100644 --- a/gcc/config/s390/2964.md +++ b/gcc/config/s390/2964.md @@ -31,7 +31,7 @@ icmy,icy,iihf,iilf,ipm,la,larl,lay,lb,lbr,lcgr,lcr,lgb,lgbr,lgf,lgfi,lgfr,\ lgfrl,lgh,lghi,lghr,lghrl,lgr,lh,lhi,lhr,lhrl,lhy,llcr,llgfr,llghr,llgtr,\ llhr,llihf,llihh,llihl,llilf,llilh,llill,lngr,lnr,loc,locg,locghi,locgr,\ lochi,locr,lpgr,lpr,lr,lrv,lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,\ -m,mfy,mghi,mh,mhi,mhy,ml,mlg,mlgr,mlr,mr,ms,msfi,msg,msgf,msgfi,msgfr,\ +mghi,mh,mhi,mhy,mlg,mlgr,ms,msfi,msg,msgf,msgfi,msgfr,\ msgr,msr,msy,n,ng,ngr,ngrk,nihf,nihh,nihl,nilf,nilh,nill,nr,nrk,ny,o,og,\ ogr,ogrk,oihf,oihh,oihl,oilf,oilh,oill,or,ork,oy,pfpo,popcnt,ppa,risbg,\ risbgn,rll,rllg,s,sg,sgf,sgfr,sgr,sgrk,sh,shy,sl,slb,slbg,slbgr,slbr,slfi,\ @@ -53,7 +53,7 @@ xiy") (const_int 1)] (const_int 0))) (define_attr "z13_unit_fxd" "" -(cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr") +(cond [(eq_attr "mnemonic" "dlgr,dsgfr,dsgr") (const_int 1)] (const_int 0))) (define_attr "z13_unit_lsu" "" @@ -63,8 +63,8 @@ chsi,chy,cl,clc,clfhsi,clg,clgf,clgfrl,clghsi,clgrl,clgt,clhhsi,clhrl,cli,\ cliy,clm,clmy,clrl,clt,cly,crl,cy,ddb,deb,ear,ic,icm,icmh,icmy,icy,l,laa,\ laag,lan,lang,lao,laog,lat,lax,laxg,lb,lcbb,ld,lde,ldeb,ldy,le,ley,lg,lgat,\ lgb,lgf,lgfrl,lgh,lghrl,lgrl,lh,lhrl,lhy,llc,llgc,llgf,llgfrl,llgh,llghrl,\ -llgt,llh,llhrl,loc,locg,lrl,lrv,lrvg,lrvh,lt,ltg,ltgf,ly,m,madb,maeb,meeb,\ -mfy,mh,mhy,ml,mlg,ms,msdb,mseb,msg,msgf,msy,mvghi,mvhhi,mvhi,mvi,mviy,n,\ +llgt,llh,llhrl,loc,locg,lrl,lrv,lrvg,lrvh,lt,ltg,ltgf,ly,madb,maeb,meeb,\ +mh,mhy,mlg,ms,msdb,mseb,msg,msgf,msy,mvghi,mvhhi,mvhi,mvi,mviy,n,\ ng,ni,niy,ntstg,ny,o,og,oi,oiy,oy,s,sar,sdb,seb,sfpc,sg,sgf,sh,shy,sl,\ slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,stey,stg,stgrl,\ sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,tabort,tm,tmy,vl,\ @@ -117,21 +117,21 @@ kdtr,kxtr,wfkdb,wfksb") (cond [(eq_attr "mnemonic" "bas,basr,cdfbr,cdftr,cdgbr,cdgtr,cdlfbr,\ cdlftr,cdlgbr,cdlgtr,cefbr,cegbr,celfbr,celgbr,cfdbr,cfebr,cfxbr,cgdbr,cgdtr,\ cgebr,cgxbr,cgxtr,chhsi,clfdbr,clfebr,clfxbr,clfxtr,clgdbr,clgdtr,clgebr,\ -clgxbr,clgxtr,cs,csg,csy,d,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,rnsbg,\ +clgxbr,clgxtr,cs,csg,csy,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,rnsbg,\ rosbg,rxsbg,stpq,vgef,vgeg,vscef,vsceg,vsteb") (const_int 1)] (const_int 0))) (define_attr "z13_expanded" "" -(cond [(eq_attr "mnemonic" "cds,cdsg,cdsy,cxfbr,cxftr,cxgbr,cxgtr,\ -cxlftr,cxlgbr,cxlgtr,dl,dlg,dsg,dsgf,lam,lm,lmg,lmy,sldl,srda,srdl,stam,stm,\ -stmg,stmy,tbegin,tbeginc") +(cond [(eq_attr "mnemonic" "cdsg,cxfbr,cxftr,cxgbr,cxgtr,\ +cxlftr,cxlgbr,cxlgtr,dlg,dsg,dsgf,lam,lmg,stam,\ +stmg,tbegin,tbeginc") (const_int 1)] (const_int 0))) (define_attr "z13_groupalone" "" (cond [(eq_attr "mnemonic" "alc,alcg,alcgr,alcr,axbr,axtr,clc,cxbr,\ -cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ -lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,ml,mlg,\ -mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,sfpc,slb,slbg,slbgr,slbr,\ +cxtr,dlgr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ +lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,madb,maeb,maebr,mlg,\ +mlgr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,sfpc,slb,slbg,slbgr,slbr,\ sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) @@ -159,8 +159,8 @@ lgr,lh,lhi,lhr,lhrl,lhy,llcr,llgfr,llghr,llgtr,llhr,llihf,llihh,llihl,\ llilf,llilh,llill,lndfr,lpdfr,lr,lrv,lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,\ ltgr,ltr,lzdr,lzer,n,ng,ngr,ngrk,nihf,nihh,nihl,nilf,nilh,nill,nop,nopr,nr,\ nrk,ny,o,og,ogr,ogrk,oihf,oihh,oihl,oilf,oilh,oill,or,ork,oy,pfpo,ppa,\ -risbg,risbgn,rll,rllg,s,sg,sgr,sgrk,sl,sldl,slfi,slg,slgf,slgfi,slgfr,slgr,\ -slgrk,sll,sllg,sllk,slr,slrk,sly,sr,sra,srag,srak,srda,srdl,srl,srlg,srlk,\ +risbg,risbgn,rll,rllg,s,sg,sgr,sgrk,sl,slfi,slg,slgf,slgfi,slgfr,slgr,\ +slgrk,sll,sllg,sllk,slr,slrk,sly,sr,sra,srag,srak,srl,srlg,srlk,\ sy,tm,tmh,tmhh,tmhl,tml,tmlh,tmll,tmy,vlr,vlvgb,vlvgf,vlvgg,vlvgh,x,xg,\ xgr,xgrk,xihf,xilf,xr,xrk,xy")) "nothing") @@ -192,8 +192,8 @@ wfchxb,wflcdb,wflcsb,wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,xi,xiy")) (define_insn_reservation "z13_2" 2 (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "cdb,cdbr,cebr,ear,ipm,l,lcbb,lcdbr,lcebr,ld,lde,\ -ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,lmg,\ -lmy,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ +ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lmg,\ +lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ vceqbs,vceqfs,vceqgs,vceqhs,vchbs,vchfs,vchgs,vchhs,vchlbs,vchlfs,vchlgs,\ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ @@ -203,7 +203,7 @@ wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing") (define_insn_reservation "z13_3" 3 (and (eq_attr "cpu" "z13") -(eq_attr "mnemonic" "cds,cdsy,std,stdy,ste,stey,vcksm,vfeezbs,\ +(eq_attr "mnemonic" "std,stdy,ste,stey,vcksm,vfeezbs,\ vfeezhs,vgfmab,vgfmaf,vgfmag,vgfmah,vgfmb,vgfmf,vgfmg,vgfmh,vistrbs,vistrfs,\ vl,vlbb,vlgvf,vlgvg,vlgvh,vll,vmaeb,vmaef,vmaeh,vmahb,vmahf,vmahh,vmalb,\ vmaleb,vmalef,vmaleh,vmalf,vmalhb,vmalhf,vmalhh,vmalhw,vmalob,vmalof,vmaloh,\ @@ -219,8 +219,8 @@ mh,mhi,mhy,mvc,oc,tabort,tbegin,tbeginc,tend,vst,vstl,xc")) "nothing") (define_insn_reservation "z13_5" 5 (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "alc,alcg,alcgr,alcr,cs,csg,csy,lngfr,lpgfr,ms,\ -msfi,msgf,msgfi,msgfr,msr,msy,rnsbg,rosbg,rxsbg,slb,slbg,slbgr,slbr,stm,\ -stmg,stmy")) "nothing") +msfi,msgf,msgfi,msgfr,msr,msy,rnsbg,rosbg,rxsbg,slb,slbg,slbgr,slbr,\ +stmg")) "nothing") (define_insn_reservation "z13_6" 6 (and (eq_attr "cpu" "z13") @@ -246,7 +246,7 @@ vfmsdb,vfmssb,vfsdb,vfssb,vldeb,vledb,kdtr")) "nothing") (define_insn_reservation "z13_10" 10 (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "cdfbr,cdgbr,cdlfbr,cdlgbr,cefbr,cegbr,celfbr,\ -celgbr,flogr,m,madb,maeb,maebr,mfy,ml,mlr,mr,msdb,mseb,msebr")) "nothing") +celgbr,flogr,madb,maeb,maebr,msdb,mseb,msebr")) "nothing") (define_insn_reservation "z13_11" 11 (and (eq_attr "cpu" "z13") @@ -269,7 +269,7 @@ ltxbr,ltxtr,lxdtr,sxbr,sxtr")) "nothing") (define_insn_reservation "z13_20" 20 (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "cdftr,cdgtr,cdlftr,cdlgtr,cgdtr,cgxtr,clfxtr,\ -clgdtr,clgxtr,cxftr,cxgtr,cxlftr,cxlgtr,d,ddb,ddbr,ddtr,deb,debr,dl,dlg,dlgr,\ -dlr,dr,dsg,dsgf,dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,\ +clgdtr,clgxtr,cxftr,cxgtr,cxlftr,cxlgtr,ddb,ddbr,ddtr,deb,debr,dlg,dlgr,\ +dsg,dsgf,dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,\ sqebr,sqxbr,vfddb,vfdsb,vfsqdb,vfsqsb,wfddb,wfdsb,wfdxb,wfsqdb,wfsqxb")) "nothing") diff --git a/gcc/config/s390/3906.md b/gcc/config/s390/3906.md index d3033c6ae472..02692cbf83d9 100644 --- a/gcc/config/s390/3906.md +++ b/gcc/config/s390/3906.md @@ -31,7 +31,7 @@ icmh,icmy,icy,iihf,iilf,ipm,la,larl,lay,lb,lbr,lcgr,lcr,lgb,lgbr,lgf,lgfi,\ lgfr,lgfrl,lgh,lghi,lghr,lghrl,lgr,lh,lhi,lhr,lhrl,lhy,llcr,llgfr,llghr,\ llgtr,llhr,llihf,llihh,llihl,llilf,llilh,llill,lngr,lnr,loc,locg,locghi,\ locgr,lochi,locr,lpgr,lpr,lr,lrv,lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,\ -ltgr,ltr,m,mfy,mg,mgh,mghi,mgrk,mh,mhi,mhy,ml,mlg,mlgr,mlr,mr,ms,msfi,msg,\ +ltgr,ltr,mg,mgh,mghi,mgrk,mh,mhi,mhy,mlg,mlgr,ms,msfi,msg,\ msgf,msgfi,msgfr,msgr,msgrkc,msr,msrkc,msy,n,ng,ngr,ngrk,nihf,nihh,nihl,\ nilf,nilh,nill,nr,nrk,ny,o,og,ogr,ogrk,oihf,oihh,oihl,oilf,oilh,oill,or,\ ork,oy,pfpo,popcnt,risbg,risbgn,rll,rllg,s,sg,sgf,sgfr,sgh,sgr,sgrk,sh,\ @@ -54,7 +54,7 @@ vstrl,vstrlr,xi,xiy") (const_int 1)] (const_int 0))) (define_attr "z14_unit_fxd" "" -(cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr") +(cond [(eq_attr "mnemonic" "dlgr,dsgfr,dsgr") (const_int 1)] (const_int 0))) (define_attr "z14_unit_lsu" "" @@ -64,8 +64,8 @@ chrl,chsi,chy,cl,clc,clfhsi,clg,clgf,clgfrl,clghsi,clgrl,clgt,clhhsi,clhrl,\ cli,cliy,clm,clmy,clrl,clt,cly,crl,cy,ddb,deb,ear,ic,icm,icmh,icmy,icy,l,\ laa,laag,lan,lang,lao,laog,lat,lax,laxg,lb,lcbb,ld,lde,ldeb,ldy,le,ley,lg,\ lgat,lgb,lgf,lgfrl,lgh,lghrl,lgrl,lh,lhrl,lhy,llc,llgc,llgf,llgfrl,llgh,\ -llghrl,llgt,llh,llhrl,loc,locg,lrl,lrv,lrvg,lrvh,lt,ltg,ltgf,ly,m,madb,maeb,\ -meeb,mfy,mg,mgh,mh,mhy,ml,mlg,ms,msdb,mseb,msg,msgf,msy,mvghi,mvhhi,mvhi,\ +llghrl,llgt,llh,llhrl,loc,locg,lrl,lrv,lrvg,lrvh,lt,ltg,ltgf,ly,madb,maeb,\ +meeb,mg,mgh,mh,mhy,mlg,ms,msdb,mseb,msg,msgf,msy,mvghi,mvhhi,mvhi,\ mvi,mviy,n,ng,ni,niy,ntstg,ny,o,og,oi,oiy,oy,s,sar,sdb,seb,sfpc,sg,sgf,\ sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,\ stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,\ @@ -121,21 +121,21 @@ vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb") (cond [(eq_attr "mnemonic" "bas,basr,cdfbr,cdftr,cdgbr,cdgtr,cdlfbr,\ cdlftr,cdlgbr,cdlgtr,cefbr,cegbr,celfbr,celgbr,cfdbr,cfebr,cfxbr,cgdbr,cgdtr,\ cgebr,cgxbr,cgxtr,chhsi,clfdbr,clfebr,clfxbr,clfxtr,clgdbr,clgdtr,clgebr,\ -clgxbr,clgxtr,cs,csg,csy,d,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,rxsbg,stpq,\ +clgxbr,clgxtr,cs,csg,csy,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,rxsbg,stpq,\ vgef,vgeg,vscef,vsceg,vsteb") (const_int 1)] (const_int 0))) (define_attr "z14_expanded" "" -(cond [(eq_attr "mnemonic" "cds,cdsg,cdsy,cxfbr,cxftr,cxgbr,cxgtr,\ -cxlftr,cxlgbr,cxlgtr,dl,dlg,dsg,dsgf,lam,lm,lmg,lmy,sldl,srda,srdl,stam,stm,\ -stmg,stmy,tbegin,tbeginc") +(cond [(eq_attr "mnemonic" "cdsg,cxfbr,cxftr,cxgbr,cxgtr,\ +cxlftr,cxlgbr,cxlgtr,dlg,dsg,dsgf,lam,lmg,stam,\ +stmg,tbegin,tbeginc") (const_int 1)] (const_int 0))) (define_attr "z14_groupalone" "" (cond [(eq_attr "mnemonic" "alc,alcg,alcgr,alcr,axbr,axtr,clc,cxbr,\ -cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ -lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\ -ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,ppa,sfpc,slb,slbg,\ +cxtr,dlgr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ +lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,madb,maeb,maebr,mg,mgrk,\ +mlg,mlgr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,ppa,sfpc,slb,slbg,\ slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) @@ -165,8 +165,8 @@ llihl,llilf,llilh,llill,lndfr,lngr,lnr,lpdfr,lpgr,lpr,lr,lrv,lrvg,lrvgr,\ lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,lzdr,lzer,n,ng,ngr,ngrk,nihf,nihh,\ nihl,nilf,nilh,nill,nop,nopr,nr,nrk,ny,o,og,ogr,ogrk,oihf,oihh,oihl,oilf,\ oilh,oill,or,ork,oy,pfpo,risbg,risbgn,rll,rllg,rnsbg,rosbg,s,sg,sgr,sgrk,\ -sl,sldl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,sly,\ -sr,sra,srag,srak,srda,srdl,srl,srlg,srlk,sy,tm,tmh,tmhh,tmhl,tml,tmlh,\ +sl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,sly,\ +sr,sra,srag,srak,srl,srlg,srlk,sy,tm,tmh,tmhh,tmhl,tml,tmlh,\ tmll,tmy,vlr,vlvgb,vlvgf,vlvgg,vlvgh,x,xg,xgr,xgrk,xihf,xilf,xr,xrk,xy")) "nothing") (define_insn_reservation "z14_1" 1 @@ -199,8 +199,8 @@ vfkesb,vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")) "nothing") (define_insn_reservation "z14_2" 2 (and (eq_attr "cpu" "z14") (eq_attr "mnemonic" "cdb,cdbr,cebr,ear,ipm,l,lcbb,lcdbr,lcebr,ld,lde,\ -ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,lmg,\ -lmy,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ +ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lmg,\ +lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ vceqbs,vceqfs,vceqgs,vceqhs,vchbs,vchfs,vchgs,vchhs,vchlbs,vchlfs,vchlgs,\ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ @@ -210,7 +210,7 @@ wfcexbs,wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing") (define_insn_reservation "z14_3" 3 (and (eq_attr "cpu" "z14") -(eq_attr "mnemonic" "cds,cdsy,mgh,mghi,mh,mhi,mhy,std,stdy,ste,stey,\ +(eq_attr "mnemonic" "mgh,mghi,mh,mhi,mhy,std,stdy,ste,stey,\ vcksm,vfeezbs,vfeezhs,vgfmab,vgfmaf,vgfmag,vgfmah,vgfmb,vgfmf,vgfmg,vgfmh,\ vistrbs,vistrfs,vl,vlbb,vll,vlrlr,vmaeb,vmaef,vmaeh,vmahb,vmahf,vmahh,vmalb,\ vmaleb,vmalef,vmaleh,vmalf,vmalhb,vmalhf,vmalhh,vmalhw,vmalob,vmalof,vmaloh,\ @@ -227,7 +227,7 @@ tbeginc,tend,vst,vstl,vstrl,vstrlr,xc")) "nothing") (define_insn_reservation "z14_5" 5 (and (eq_attr "cpu" "z14") (eq_attr "mnemonic" "alc,alcg,alcgr,alcr,cs,csg,csy,msrkc,slb,slbg,\ -slbgr,slbr,stm,stmg,stmy")) "nothing") +slbgr,slbr,stmg")) "nothing") (define_insn_reservation "z14_6" 6 (and (eq_attr "cpu" "z14") @@ -249,7 +249,7 @@ vfasb,vfisb,vfmasb,vfmsb,vfmssb,vfnmssb,vfssb,vgef,vgeg,wflld,kdtr")) (define_insn_reservation "z14_9" 9 (and (eq_attr "cpu" "z14") -(eq_attr "mnemonic" "cxfbr,cxgbr,cxlgbr,m,mfy,ml,mlr,mr,stam,wfaxb,\ +(eq_attr "mnemonic" "cxfbr,cxgbr,cxlgbr,stam,wfaxb,\ wfixb,wfsxb")) "nothing") (define_insn_reservation "z14_10" 10 @@ -278,8 +278,8 @@ ltxbr,ltxtr,lxdtr,sxbr,sxtr")) "nothing") (define_insn_reservation "z14_20" 20 (and (eq_attr "cpu" "z14") (eq_attr "mnemonic" "cdftr,cdgtr,cdlftr,cdlgtr,cgdtr,cgxtr,clfxtr,\ -clgdtr,clgxtr,cxftr,cxgtr,cxlftr,cxlgtr,d,ddb,ddbr,ddtr,deb,debr,dl,dlg,dlgr,\ -dlr,dr,dsg,dsgf,dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,\ +clgdtr,clgxtr,cxftr,cxgtr,cxlftr,cxlgtr,ddb,ddbr,ddtr,deb,debr,dlg,dlgr,\ +dsg,dsgf,dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,\ sqebr,sqxbr,vfddb,vfdsb,vfsqdb,vfsqsb,wfddb,wfdsb,wfdxb,wfmaxb,wfmsxb,wfmxb,\ wfnmaxb,wfnmsxb,wfsqdb,wfsqxb")) "nothing") diff --git a/gcc/config/s390/3931.md b/gcc/config/s390/3931.md index c5b93f8d0db1..11c67ab6fd2f 100644 --- a/gcc/config/s390/3931.md +++ b/gcc/config/s390/3931.md @@ -149,8 +149,6 @@ ltgf, ltgfr, ltgr, ltr, -m, -mfy, mg, mgh, mghi, @@ -158,11 +156,8 @@ mgrk, mh, mhi, mhy, -ml, mlg, mlgr, -mlr, -mr, ms, msc, msfi, @@ -426,8 +421,6 @@ xiy" (define_attr "z16_unit_fxd" "" (cond [(eq_attr "mnemonic" "dlgr, -dlr, -dr, dsgfr, dsgr" ) @@ -547,17 +540,14 @@ lt, ltg, ltgf, ly, -m, madb, maeb, mdb, meeb, -mfy, mg, mgh, mh, mhy, -ml, mlg, ms, msc, @@ -1233,7 +1223,6 @@ clgxtr, cs, csg, csy, -d, efpc, ex, lcgfr, @@ -1256,9 +1245,7 @@ vsteh" (define_attr "z16_expanded" "" (cond [(eq_attr "mnemonic" -"cds, -cdsg, -cdsy, +"cdsg, cxfbr, cxftr, cxgbr, @@ -1267,21 +1254,13 @@ cxlfbr, cxlftr, cxlgbr, cxlgtr, -dl, dlg, dsg, dsgf, lam, -lm, lmg, -lmy, -sldl, -srda, -srdl, stam, -stm, stmg, -stmy, tbegin, tbeginc" ) @@ -1299,8 +1278,6 @@ clc, cxbr, cxtr, dlgr, -dlr, -dr, dsgfr, dsgr, dxbr, @@ -1321,18 +1298,13 @@ lxdbr, lxdtr, lxeb, lxebr, -m, madb, maeb, maebr, -mfy, mg, mgrk, -ml, mlg, mlgr, -mlr, -mr, msdb, mseb, msebr, @@ -1620,7 +1592,6 @@ sg, sgr, sgrk, sl, -sldl, slfi, slg, slgf, @@ -1638,8 +1609,6 @@ sr, sra, srag, srak, -srda, -srdl, srk, srl, srlg, @@ -2028,9 +1997,7 @@ llghrl, llgt, llh, llhrl, -lm, lmg, -lmy, lndbr, lnebr, lpdbr, @@ -2117,9 +2084,7 @@ wftcixb" (define_insn_reservation "z16_3" 3 (and (eq_attr "cpu" "z16") (eq_attr "mnemonic" -"cds, -cdsy, -mgh, +"mgh, mghi, mh, mhi, @@ -2290,9 +2255,7 @@ slb, slbg, slbgr, slbr, -stm, stmg, -stmy, vcdgb, vcdlgb, vcefb, @@ -2398,14 +2361,9 @@ cxfbr, cxgbr, cxlfbr, cxlgbr, -m, madb, maeb, maebr, -mfy, -ml, -mlr, -mr, msdb, mseb, msebr, @@ -2505,17 +2463,13 @@ clgdtr, clgxtr, cxgtr, cxlgtr, -d, ddb, ddbr, ddtr, deb, debr, -dl, dlg, dlgr, -dlr, -dr, dsg, dsgf, dsgfr, diff --git a/gcc/config/s390/8561.md b/gcc/config/s390/8561.md index 07797001f2d9..2c49094c2349 100644 --- a/gcc/config/s390/8561.md +++ b/gcc/config/s390/8561.md @@ -30,8 +30,8 @@ ic,icm,icmh,icmy,icy,iihf,iilf,ipm,la,larl,lay,lb,lbr,lcgr,lcr,lgb,lgbr,\ lgf,lgfi,lgfr,lgfrl,lgh,lghi,lghr,lghrl,lgr,lh,lhi,lhr,lhrl,lhy,llcr,\ llgcr,llgfr,llghr,llgtr,llhr,llihf,llihh,llihl,llilf,llilh,llill,lngr,lnr,\ loc,locg,locghi,locgr,lochi,locr,lpgr,lpr,lr,lrv,lrvg,lrvgr,lrvh,lrvr,lt,\ -ltg,ltgf,ltgfr,ltgr,ltr,m,mfy,mg,mgh,mghi,mgrk,mh,mhi,mhy,ml,mlg,mlgr,mlr,\ -mr,ms,msfi,msg,msgf,msgfi,msgfr,msgr,msgrkc,msr,msrkc,msy,n,ng,ngr,ngrk,\ +ltg,ltgf,ltgfr,ltgr,ltr,mg,mgh,mghi,mgrk,mh,mhi,mhy,mlg,mlgr,\ +ms,msfi,msg,msgf,msgfi,msgfr,msgr,msgrkc,msr,msrkc,msy,n,ng,ngr,ngrk,\ nihf,nihh,nihl,nilf,nilh,nill,nr,nrk,ny,o,og,ogr,ogrk,oihf,oihh,oihl,oilf,\ oilh,oill,or,ork,oy,pfpo,popcnt,risbg,risbgn,rll,rllg,s,sg,sgf,sgfr,sgh,\ sgr,sgrk,sh,shy,sl,slb,slbg,slbgr,slbr,slfi,slg,slgf,slgfi,slgfr,slgr,\ @@ -53,7 +53,7 @@ vlvgp,vst,vstef,vsteg,vstl,vstrl,vstrlr,xi,xiy") (const_int 1)] (const_int 0))) (define_attr "z15_unit_fxd" "" -(cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr") +(cond [(eq_attr "mnemonic" "dlgr,dsgfr,dsgr") (const_int 1)] (const_int 0))) (define_attr "z15_unit_lsu" "" @@ -64,7 +64,7 @@ clgt,clhhsi,clhrl,cli,cliy,clm,clmy,clrl,clt,cly,crl,cy,ddb,deb,ear,ic,icm,\ icmh,icmy,icy,l,laa,laag,lan,lang,lao,laog,lat,lax,laxg,lb,lcbb,ld,lde,\ ldeb,ldy,le,ley,lg,lgat,lgb,lgf,lgfrl,lgh,lghrl,lgrl,lh,lhrl,lhy,llc,llgc,\ llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,loc,locg,lrl,lrv,lrvg,lrvh,lt,ltg,\ -ltgf,ly,m,madb,maeb,mdb,meeb,mfy,mg,mgh,mh,mhy,ml,mlg,ms,msdb,mseb,msg,\ +ltgf,ly,madb,maeb,mdb,meeb,mg,mgh,mh,mhy,mlg,ms,msdb,mseb,msg,\ msgf,msy,mvghi,mvhhi,mvhi,mvi,mviy,n,ng,ni,niy,ntstg,ny,o,og,oi,oiy,oy,s,\ sar,sdb,seb,sfpc,sg,sgf,sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,\ stc,stcy,std,stdy,ste,stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,\ @@ -121,21 +121,21 @@ vfkhedb,wfkhexb") (cond [(eq_attr "mnemonic" "bas,basr,cdfbr,cdftr,cdgbr,cdgtr,cdlfbr,\ cdlftr,cdlgbr,cdlgtr,cefbr,cegbr,celfbr,celgbr,cfdbr,cfebr,cfxbr,cgdbr,cgdtr,\ cgebr,cgxbr,cgxtr,chhsi,clfdbr,clfdtr,clfebr,clfxbr,clfxtr,clgdbr,clgdtr,\ -clgebr,clgxbr,clgxtr,cs,csg,csy,d,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,\ +clgebr,clgxbr,clgxtr,cs,csg,csy,efpc,ex,lcgfr,lngfr,lpgfr,lpq,lxr,lzxr,\ rxsbg,stpq,vgef,vgeg,vscef,vsceg,vsteb,vsteh") (const_int 1)] (const_int 0))) (define_attr "z15_expanded" "" -(cond [(eq_attr "mnemonic" "cds,cdsg,cdsy,cxfbr,cxftr,cxgbr,cxgtr,\ -cxlfbr,cxlftr,cxlgbr,cxlgtr,dl,dlg,dsg,dsgf,lam,lm,lmg,lmy,sldl,srda,srdl,\ -stam,stm,stmg,stmy,tbegin,tbeginc") +(cond [(eq_attr "mnemonic" "cdsg,cxfbr,cxftr,cxgbr,cxgtr,\ +cxlfbr,cxlftr,cxlgbr,cxlgtr,dlg,dsg,dsgf,lam,lmg,\ +stam,stmg,tbegin,tbeginc") (const_int 1)] (const_int 0))) (define_attr "z15_groupalone" "" (cond [(eq_attr "mnemonic" "alc,alcg,alcgr,alcr,axbr,axtr,clc,cxbr,\ -cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ -lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\ -ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,nc,oc,ppa,sfpc,slb,slbg,\ +cxtr,dlgr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ +lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,madb,maeb,maebr,mg,mgrk,\ +mlg,mlgr,msdb,mseb,msebr,mvc,mxbr,mxtr,nc,oc,ppa,sfpc,slb,slbg,\ slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) @@ -165,8 +165,8 @@ llhr,llihf,llihh,llihl,llilf,llilh,llill,lndfr,lngr,lnr,lpdfr,lpgr,lpr,lr,\ lrv,lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,lzdr,lzer,n,ng,ngr,\ ngrk,nihf,nihh,nihl,nilf,nilh,nill,nop,nopr,nr,nrk,ny,o,og,ogr,ogrk,oihf,\ oihh,oihl,oilf,oilh,oill,or,ork,oy,pfpo,risbg,risbgn,rll,rllg,rnsbg,rosbg,\ -s,sg,sgr,sgrk,sl,sldl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,\ -sllk,slr,slrk,sly,sr,sra,srag,srak,srda,srdl,srk,srl,srlg,srlk,sy,tm,tmh,\ +s,sg,sgr,sgrk,sl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,\ +sllk,slr,slrk,sly,sr,sra,srag,srak,srk,srl,srlg,srlk,sy,tm,tmh,\ tmhh,tmhl,tml,tmlh,tmll,tmy,vlr,vlvgb,vlvgf,vlvgg,vlvgh,x,xg,xgr,xgrk,xihf,\ xilf,xr,xrk,xy")) "nothing") @@ -202,8 +202,8 @@ xiy,vfkesb,vfkedb,wfkexb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")) (define_insn_reservation "z15_2" 2 (and (eq_attr "cpu" "z15") (eq_attr "mnemonic" "cdb,cdbr,ceb,cebr,ear,ipm,l,lcbb,lcdbr,lcebr,ld,\ -lde,ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,\ -lmg,lmy,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ +lde,ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,\ +lmg,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\ vceqbs,vceqfs,vceqgs,vceqhs,vchbs,vchfs,vchgs,vchhs,vchlbs,vchlfs,vchlgs,\ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ @@ -214,7 +214,7 @@ wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb,keb,kebr,kdb,kdbr,wfkdb,wfksb")) (define_insn_reservation "z15_3" 3 (and (eq_attr "cpu" "z15") -(eq_attr "mnemonic" "cds,cdsy,mgh,mghi,mh,mhi,mhy,std,stdy,ste,stey,\ +(eq_attr "mnemonic" "mgh,mghi,mh,mhi,mhy,std,stdy,ste,stey,\ vcksm,vfeezbs,vfeezfs,vfeezhs,vgfmab,vgfmaf,vgfmag,vgfmah,vgfmb,vgfmf,vgfmg,\ vgfmh,vistrbs,vistrfs,vistrhs,vl,vlbb,vll,vlrlr,vmaeb,vmaef,vmaeh,vmahb,\ vmahf,vmahh,vmalb,vmaleb,vmalef,vmaleh,vmalf,vmalhb,vmalhf,vmalhh,vmalhw,\ @@ -232,7 +232,7 @@ tbeginc,tend,vst,vstef,vsteg,vstl,vstrl,vstrlr,xc")) "nothing") (and (eq_attr "cpu" "z15") (eq_attr "mnemonic" "adb,adbr,aeb,aebr,alc,alcg,alcgr,alcr,cs,csg,\ csy,fidbr,fidbra,fiebr,fiebra,ldeb,ldebr,ledbr,madbr,mdb,mdbr,meeb,meebr,\ -msdbr,msrkc,sdb,sdbr,seb,sebr,slb,slbg,slbgr,slbr,stm,stmg,stmy,vfadb,vfasb,\ +msdbr,msrkc,sdb,sdbr,seb,sebr,slb,slbg,slbgr,slbr,stmg,vfadb,vfasb,\ vfidb,vfisb,vfmadb,vfmasb,vfmdb,vfmsb,vfmsdb,vfmssb,vfnmadb,vfnmasb,vfnmsdb,\ vfnmssb,vfsdb,vfssb,vldeb,vledb,vmslg,wfadb,wfasb,wfidb,wfisb,wflld,wfmadb,\ wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing") @@ -253,7 +253,7 @@ tdcet,vgef,vgeg,kdtr")) "nothing") (define_insn_reservation "z15_9" 9 (and (eq_attr "cpu" "z15") (eq_attr "mnemonic" "cdfbr,cdgbr,cdlfbr,cdlgbr,cefbr,cegbr,celfbr,\ -celgbr,cxfbr,cxgbr,cxlfbr,cxlgbr,m,madb,maeb,maebr,mfy,ml,mlr,mr,msdb,mseb,\ +celgbr,cxfbr,cxgbr,cxlfbr,cxlgbr,madb,maeb,maebr,msdb,mseb,\ msebr,stam,wfaxb,wfixb,wfsxb")) "nothing") (define_insn_reservation "z15_10" 10 @@ -286,7 +286,7 @@ ltxbr,ltxtr,lxdtr,sxbr,sxtr")) "nothing") (define_insn_reservation "z15_20" 20 (and (eq_attr "cpu" "z15") (eq_attr "mnemonic" "cdgtr,cdlgtr,cgdtr,cgxtr,clfdtr,clfxtr,clgdtr,\ -clgxtr,cxgtr,cxlgtr,d,ddb,ddbr,ddtr,deb,debr,dl,dlg,dlgr,dlr,dr,dsg,dsgf,\ +clgxtr,cxgtr,cxlgtr,ddb,ddbr,ddtr,deb,debr,dlg,dlgr,dsg,dsgf,\ dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,sqebr,sqxbr,vfddb,\ vfdsb,vfsqdb,vfsqsb,wfddb,wfdsb,wfdxb,wfmaxb,wfmsxb,wfmxb,wfnmaxb,wfnmsxb,\ wfsqdb,wfsqxb")) "nothing") diff --git a/gcc/config/s390/9175.md b/gcc/config/s390/9175.md index e39da829edeb..9d770092a302 100644 --- a/gcc/config/s390/9175.md +++ b/gcc/config/s390/9175.md @@ -31,14 +31,14 @@ icmh,icmy,icy,iihf,iilf,ipm,la,larl,lay,lb,lbr,lcgfr,lcgr,lcr,lgb,lgbr,lgf,\ lgfi,lgfr,lgfrl,lgh,lghi,lghr,lghrl,lgr,lh,lhi,lhr,lhrl,lhy,llcr,llgcr,llgfr,\ llghr,llgtr,llhr,llihf,llihh,llihl,llilf,llilh,llill,llxab,llxaf,llxag,llxah,\ llxaq,lngfr,lngr,lnr,loc,locg,locghi,locgr,lochi,locr,lpgfr,lpgr,lpr,lr,lrv,\ -lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,lxab,lxaf,lxag,lxah,lxaq,m,mfy,\ -mg,mgh,mghi,mgrk,mh,mhi,mhy,ml,mlg,mlgr,mlr,mr,ms,msc,msfi,msg,msgc,msgf,msgfi,\ +lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,lxab,lxaf,lxag,lxah,lxaq,\ +mg,mgh,mghi,mgrk,mh,mhi,mhy,mlg,mlgr,ms,msc,msfi,msg,msgc,msgf,msgfi,\ msgfr,msgr,msgrkc,msr,msrkc,msy,n,ncgrk,ncrk,ng,ngr,ngrk,nihf,nihh,nihl,nilf,\ nilh,nill,nngrk,nnrk,nogrk,nork,nr,nrk,nxgrk,nxrk,ny,o,ocgrk,ocrk,og,ogr,ogrk,\ oihf,oihh,oihl,oilf,oilh,oill,or,ork,oy,pfpo,popcnt,risbg,risbgn,rll,rllg,\ rnsbg,rosbg,rxsbg,s,selgr,selr,sg,sgf,sgfr,sgh,sgr,sgrk,sh,shy,sl,slb,slbg,\ -slbgr,slbr,sldl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,\ -sly,sr,sra,srag,srak,srda,srdl,srk,srl,srlg,srlk,sy,x,xg,xgr,xgrk,xihf,xilf,xr,\ +slbgr,slbr,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,\ +sly,sr,sra,srag,srak,srk,srl,srlg,srlk,sy,x,xg,xgr,xgrk,xihf,xilf,xr,\ xrk,xy") (const_int 1)] (const_int 0))) @@ -57,12 +57,12 @@ xiy") (const_int 1)] (const_int 0))) (define_attr "z17_unit_fxd" "" - (cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr") + (cond [(eq_attr "mnemonic" "dlgr,dsgfr,dsgr") (const_int 1)] (const_int 0))) (define_attr "z17_unit_lsu" "" (cond [(eq_attr "mnemonic" "clc,ear,l,lam,lcbb,ld,lde,ldy,lg,lgrl,llc,llgc,\ -llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,lmg,lmy,lpq,lrl,ly,mvcrl,sar,sfpc,\ +llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lmg,lpq,lrl,ly,mvcrl,sar,sfpc,\ tabort,vl,vlbb,vlbrf,vlbrg,vlbrh,vlbrq,vlbrrepf,vlbrrepg,vlbrreph,vlerf,vlerg,\ vlerh,vll,vllebrzf,vllebrzg,vllebrzh,vllezb,vllezf,vllezg,vllezh,vllezlf,\ vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr") @@ -127,23 +127,23 @@ mvc,nc,oc,rnsbg,rosbg,rxsbg,stpq,vgef,vgeg,vscef,vsceg,vsteb,vstebrh,vsteh,xc") (const_int 1)] (const_int 0))) (define_attr "z17_expanded" "" - (cond [(eq_attr "mnemonic" "cds,cdsg,cdsy,cxfbr,cxftr,cxgbr,cxgtr,cxlfbr,\ -cxlftr,cxlgbr,cxlgtr,d,dl,dlg,dsg,dsgf,lam,lm,lmg,lmy,sldl,srda,srdl,stam,stm,\ -stmg,stmy,tbegin,tbeginc") + (cond [(eq_attr "mnemonic" "cdsg,cxfbr,cxftr,cxgbr,cxgtr,cxlfbr,\ +cxlftr,cxlgbr,cxlgtr,dlg,dsg,dsgf,lam,lmg,stam,\ +stmg,tbegin,tbeginc") (const_int 1)] (const_int 0))) (define_attr "z17_groupalone" "" (cond [(eq_attr "mnemonic" "alc,alcg,alcgr,alcr,axbr,axtr,clc,cxbr,cxfbr,\ -cxftr,cxgbr,cxgtr,cxlfbr,cxlftr,cxlgbr,cxlgtr,cxtr,d,dl,dlg,dlgr,dlr,dr,dsg,\ +cxftr,cxgbr,cxgtr,cxlfbr,cxlftr,cxlgbr,cxlgtr,cxtr,dlg,dlgr,dsg,\ dsgf,dsgfr,dsgr,dxbr,dxtr,ex,exrl,fixbr,fixbra,fixtr,flogr,kxbr,kxtr,lcxbr,\ -lnxbr,lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,\ -mgrk,ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mvcrl,mxbr,mxtr,nc,oc,ppa,sfpc,slb,\ +lnxbr,lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,madb,maeb,maebr,mg,\ +mgrk,mlg,mlgr,msdb,mseb,msebr,mvc,mvcrl,mxbr,mxtr,nc,oc,ppa,sfpc,slb,\ slbg,slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tbegin,tbeginc,tcxb,tdcxt,tend,xc") (const_int 1)] (const_int 0))) (define_attr "z17_endgroup" "" (cond [(eq_attr "mnemonic" "bas,basr,bcr,br,bras,brasl,cdsg,clfebr,cs,csg,csy,\ -efpc,ex,exrl,ipm,lam,lpq,lxr,nopr,sldl,srda,srdl,stam,stm,stmg,stmy,tbegin,\ +efpc,ex,exrl,ipm,lam,lpq,lxr,nopr,stam,stmg,tbegin,\ tbeginc") (const_int 1)] (const_int 0))) @@ -173,9 +173,9 @@ llcr,llgcr,llgfr,llghr,llgtr,llhr,llihf,llihh,llihl,llilf,llilh,llill,lndfr,\ lngr,lnr,lpdfr,lpgr,lpr,lr,lrv,lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,\ lzdr,lzer,n,ncgrk,ncrk,ng,ngr,ngrk,nihf,nihh,nihl,nilf,nilh,nill,nngrk,nnrk,\ nogrk,nop,nopr,nork,nr,nrk,nxgrk,nxrk,ny,o,ocgrk,ocrk,og,ogr,ogrk,oihf,oihh,\ -oihl,oilf,oilh,oill,or,ork,oy,pfpo,risbg,risbgn,rll,rllg,s,sg,sgr,sgrk,sl,sldl,\ +oihl,oilf,oilh,oill,or,ork,oy,pfpo,risbg,risbgn,rll,rllg,s,sg,sgr,sgrk,sl,\ slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,sly,sr,sra,srag,\ -srak,srda,srdl,srk,srl,srlg,srlk,sy,tm,tmh,tmhh,tmhl,tml,tmlh,tmll,tmy,vlr,\ +srak,srk,srl,srlg,srlk,sy,tm,tmh,tmhh,tmhl,tml,tmlh,tmll,tmy,vlr,\ vlvgb,vlvgf,vlvgg,vlvgh,x,xg,xgr,xgrk,xihf,xilf,xr,xrk,xy")) "nothing") (define_insn_reservation "z17_1" 1 @@ -217,7 +217,7 @@ xi,xiy")) "nothing") (and (eq_attr "cpu" "z17") (eq_attr "mnemonic" "cdb,cdbr,ceb,cebr,clzg,ctzg,ear,ipm,kdb,kdbr,keb,kebr,l,\ lcbb,lcdbr,lcebr,ld,lde,ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,\ -llh,llhrl,lm,lmg,lmy,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,\ +llh,llhrl,lmg,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,\ tcdb,tceb,vfeeb,vfeef,vfeeh,vfeezbs,vfeezfs,vfeezhs,vfeneb,vfenef,vfeneh,\ vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrbs,vistrf,vistrfs,vistrh,\ vistrhs,vlbrrepf,vlbrrepg,vlbrreph,vlgvb,vlgvf,vlgvg,vlgvh,vllebrzf,vllebrzg,\ @@ -226,7 +226,7 @@ vlvgp,wfcdb,wfcsb,wfcxb,wfkdb,wfksb,wfkxb,wftcixb")) "nothing") (define_insn_reservation "z17_3" 3 (and (eq_attr "cpu" "z17") - (eq_attr "mnemonic" "bdepg,bextg,cds,cdsy,mgh,mghi,mh,mhi,mhy,ms,msc,msfi,msg,\ + (eq_attr "mnemonic" "bdepg,bextg,mgh,mghi,mh,mhi,mhy,ms,msc,msfi,msg,\ msgc,msgf,msgfi,msgfr,msgr,msgrkc,msr,msrkc,msy,std,stdy,ste,stey,vcksm,vgfmab,\ vgfmaf,vgfmag,vgfmah,vgfmb,vgfmf,vgfmg,vgfmh,vl,vlbb,vlbrf,vlbrg,vlbrh,vlbrq,\ vlerf,vlerg,vlerh,vll,vlrlr,vmaeb,vmaef,vmaeg,vmaeh,vmahb,vmahf,vmahg,vmahh,\ @@ -247,7 +247,7 @@ vstrlr")) "nothing") (and (eq_attr "cpu" "z17") (eq_attr "mnemonic" "adb,adbr,aeb,aebr,alc,alcg,alcgr,alcr,cs,csg,csy,fidbr,\ fidbra,fiebr,fiebra,ldeb,ldebr,ledbr,madbr,mdb,mdbr,meeb,meebr,msdbr,sdb,sdbr,\ -seb,sebr,slb,slbg,slbgr,slbr,stm,stmg,stmy,vcdgb,vcdlgb,vcefb,vcelfb,vcfeb,\ +seb,sebr,slb,slbg,slbgr,slbr,stmg,vcdgb,vcdlgb,vcefb,vcelfb,vcfeb,\ vcgdb,vclfeb,vclgdb,vldeb,vledb,vmslg,wcdgb,wcdlgb,wcefb,wcelfb,wcfeb,wcgdb,\ wclfeb,wclgdb,wflld,wflrx,wldeb,wledb")) "nothing") @@ -263,8 +263,8 @@ wfsdb,wfssb,wfsxb")) "nothing") (define_insn_reservation "z17_8" 8 (and (eq_attr "cpu" "z17") - (eq_attr "mnemonic" "cdgtr,cdlgtr,cdsg,cxgtr,cxlgtr,flogr,lpq,m,mfy,mg,mgrk,\ -ml,mlg,mlgr,mlr,mr,stpq,vsteb,vstebrh,vsteh")) "nothing") + (eq_attr "mnemonic" "cdgtr,cdlgtr,cdsg,cxgtr,cxlgtr,flogr,lpq,mg,mgrk,\ +mlg,mlgr,stpq,vsteb,vstebrh,vsteh")) "nothing") (define_insn_reservation "z17_9" 9 (and (eq_attr "cpu" "z17") @@ -273,7 +273,7 @@ maeb,maebr,msdb,mseb,msebr,stam")) "nothing") (define_insn_reservation "z17_10" 10 (and (eq_attr "cpu" "z17") - (eq_attr "mnemonic" "cgdtr,cgxtr,clfdtr,clfxtr,clgdtr,clgxtr,d,dl,dlg,dsg,\ + (eq_attr "mnemonic" "cgdtr,cgxtr,clfdtr,clfxtr,clgdtr,clgxtr,dlg,dsg,\ dsgf,efpc,lxdb,lxdbr,lxeb,lxebr,vscef,vsceg")) "nothing") (define_insn_reservation "z17_11" 11 @@ -307,7 +307,7 @@ lcxbr,lnxbr,lpxbr,ltxbr,ltxtr,lxdtr,sxbr,sxtr")) "nothing") (define_insn_reservation "z17_20" 20 (and (eq_attr "cpu" "z17") - (eq_attr "mnemonic" "ddb,ddbr,ddtr,deb,debr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,\ + (eq_attr "mnemonic" "ddb,ddbr,ddtr,deb,debr,dlgr,dsgfr,dsgr,dxbr,dxtr,\ mdtr,mvc,mxbr,mxtr,sqdb,sqdbr,sqeb,sqebr,sqxbr,vdf,vdg,vdlf,vdlg,vdlq,vdq,\ vfddb,vfdsb,vfmadb,vfmasb,vfmdb,vfmsb,vfmsdb,vfmssb,vfnmadb,vfnmasb,vfnmsdb,\ vfnmssb,vfsqdb,vfsqsb,vrf,vrg,vrlf,vrlg,vrlq,vrq,wfddb,wfdsb,wfdxb,wfmadb,\ diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md index 62ea3013ff4b..be57b43b0015 100644 --- a/gcc/config/s390/constraints.md +++ b/gcc/config/s390/constraints.md @@ -583,8 +583,8 @@ (match_test "s390_mem_constraint (\"ZT\", op)")) (define_constraint "ZL" - "LARL operand when in 64-bit mode, otherwise nothing." - (match_test "TARGET_64BIT && larl_operand (op, VOIDmode)")) + "LARL operand." + (match_test "larl_operand (op, VOIDmode)")) ;; This constraint must behave like "i", in particular, the matching values ;; must never be placed into registers or memory by diff --git a/gcc/config/s390/driver-native.cc b/gcc/config/s390/driver-native.cc index 07333249224d..8ddb51ced1ef 100644 --- a/gcc/config/s390/driver-native.cc +++ b/gcc/config/s390/driver-native.cc @@ -48,12 +48,9 @@ s390_host_detect_local_cpu (int argc, const char **argv) unsigned int has_features; unsigned int has_processor; unsigned int is_cpu_z9_109 = 0; - unsigned int has_highgprs = 0; unsigned int has_dfp = 0; unsigned int has_te = 0; unsigned int has_vx = 0; - unsigned int has_opt_esa_zarch = 0; - int i; if (argc < 1) return NULL; @@ -61,9 +58,6 @@ s390_host_detect_local_cpu (int argc, const char **argv) arch = strcmp (argv[0], "arch") == 0; if (!arch && strcmp (argv[0], "tune")) return NULL; - for (i = 1; i < argc; i++) - if (strcmp (argv[i], "mesa_mzarch") == 0) - has_opt_esa_zarch = 1; f = fopen ("/proc/cpuinfo", "r"); if (f == NULL) @@ -158,8 +152,6 @@ s390_host_detect_local_cpu (int argc, const char **argv) has_te = 1; else if (i == 2 && startswith (p, "vx")) has_vx = 1; - else if (i == 8 && startswith (p, "highgprs")) - has_highgprs = 1; p += i; } has_features = 1; @@ -175,7 +167,6 @@ s390_host_detect_local_cpu (int argc, const char **argv) { const char *opt_htm = ""; const char *opt_vx = ""; - const char *opt_esa_zarch = ""; /* We may switch off these cpu features but never switch the on explicitly. This overrides options specified on the command line. */ @@ -183,12 +174,7 @@ s390_host_detect_local_cpu (int argc, const char **argv) opt_htm = " -mno-htm"; if (!has_vx) opt_vx = " -mno-vx"; - /* However, we set -mzarch only if neither -mzarch nor -mesa are used on - the command line. This allows the user to switch to -mesa manually. - */ - if (!has_opt_esa_zarch && has_highgprs) - opt_esa_zarch = " -mzarch"; - options = concat (options, opt_htm, opt_vx, opt_esa_zarch, NULL); + options = concat (options, opt_htm, opt_vx, NULL); } if (has_dfp && is_cpu_z9_109) cpu = "z9-ec"; diff --git a/gcc/config/s390/htmxlintrin.h b/gcc/config/s390/htmxlintrin.h index 74182fc89c0b..9a9e00f82db1 100644 --- a/gcc/config/s390/htmxlintrin.h +++ b/gcc/config/s390/htmxlintrin.h @@ -167,11 +167,7 @@ extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artific __TM_failure_address (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; -#ifdef __s390x__ return tdb->atia; -#else - return tdb->atia & 0xffffffff; -#endif } extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h index b836d566a7c7..b95bb48f405b 100644 --- a/gcc/config/s390/linux.h +++ b/gcc/config/s390/linux.h @@ -24,14 +24,10 @@ along with GCC; see the file COPYING3. If not see /* Target specific type definitions. */ -/* For 31 bit our size type differs from most other targets (where it - is "unsigned int"). The difference tends to cause trouble e.g.: - Glibc BZ #16712, GCC BZ #79358 but cannot be changed due to ABI - issues. */ #undef SIZE_TYPE #define SIZE_TYPE "long unsigned int" #undef PTRDIFF_TYPE -#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int") +#define PTRDIFF_TYPE "long int" #undef WCHAR_TYPE #define WCHAR_TYPE "int" @@ -51,10 +47,13 @@ along with GCC; see the file COPYING3. If not see /* Target specific assembler settings. */ /* Rewrite -march=arch* options to the original CPU name in order to - make it work with older binutils. */ + make it work with older binutils. The spec is incomplete in the sense that + it passes -march=z* but filters -march=archX with X>11 out. However, + starting with binutils 2.22 the .machine pseudo-op is supported which + overrides command line option -march anyway. */ #undef ASM_SPEC #define ASM_SPEC \ - "%{m31&m64}%{mesa&mzarch}%{march=z*}" \ + "%{march=z*}" \ "%{march=arch5:-march=z900}" \ "%{march=arch6:-march=z990}" \ "%{march=arch7:-march=z9-ec}" \ @@ -66,30 +65,22 @@ along with GCC; see the file COPYING3. If not see /* Target specific linker settings. */ -#ifdef DEFAULT_TARGET_64BIT #define MULTILIB_DEFAULTS { "m64" } -#else -#define MULTILIB_DEFAULTS { "m31" } -#endif -#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" -#undef MUSL_DYNAMIC_LINKER32 -#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" #undef MUSL_DYNAMIC_LINKER64 #define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" #undef LINK_SPEC #define LINK_SPEC \ - "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ + "-m elf64_s390 \ %{shared:-shared} \ %{!shared: \ %{static:-static} \ %{!static:%{!static-pie: \ %{rdynamic:-export-dynamic} \ - %{m31:-dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "} \ - %{m64:-dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}}} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}} \ %{static-pie:-static -pie --no-dynamic-linker -z text}" #define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" @@ -97,9 +88,7 @@ along with GCC; see the file COPYING3. If not see #define TARGET_ASM_FILE_END file_end_indicate_exec_stack #ifdef TARGET_LIBC_PROVIDES_SSP -/* s390 glibc provides __stack_chk_guard in 0x14(tp), - s390x glibc provides it at 0x28(tp). */ -#define TARGET_THREAD_SSP_OFFSET (TARGET_64BIT ? 0x28 : 0x14) +#define TARGET_THREAD_SSP_OFFSET 0x28 #endif /* Define if long doubles should be mangled as 'g'. */ diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index 2c29e78c2416..b5e6da0f0945 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -97,17 +97,12 @@ }) ;; Return true if OP is a valid operand for the BRAS instruction. -;; Allow SYMBOL_REFs and @PLT stubs. (define_special_predicate "bras_sym_operand" - (ior (and (match_code "symbol_ref") - (ior (match_test "!flag_pic") - (match_test "SYMBOL_REF_LOCAL_P (op)") - (and (match_test "TARGET_64BIT") - (match_test "SYMBOL_REF_FUNCTION_P (op)")))) - (and (match_code "const") - (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") - (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT31"))))) + (and (match_code "symbol_ref") + (ior (match_test "!flag_pic") + (match_test "SYMBOL_REF_LOCAL_P (op)") + (match_test "SYMBOL_REF_FUNCTION_P (op)")))) ;; Return true if OP is a PLUS that is not a legitimate ;; operand for the LA instruction. @@ -199,9 +194,6 @@ if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_GOTENT) return true; - if (GET_CODE (op) == UNSPEC - && XINT (op, 1) == UNSPEC_PLT31) - return true; if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_INDNTPOFF) return true; diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index d3d581792f3b..90b52ba204ab 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -718,8 +718,8 @@ OB_DEF_VAR (s390_vec_scatter_element_u64,s390_vsceg, 0, OB_DEF_VAR (s390_vec_scatter_element_flt,s390_vscef, B_VXE, O4_U2, BT_OV_VOID_V4SF_UV4SI_FLTPTR_ULONGLONG) OB_DEF_VAR (s390_vec_scatter_element_dbl,s390_vsceg, 0, O4_U1, BT_OV_VOID_V2DF_UV2DI_DBLPTR_ULONGLONG) -B_DEF (s390_vscef, vec_scatter_elementv4si,0, B_VX, O4_U2, BT_FN_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG) -B_DEF (s390_vsceg, vec_scatter_elementv2di,0, B_VX, O4_U1, BT_FN_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG) +B_DEF (s390_vscef, vec_scatter_elementv4si_DI,0, B_VX, O4_U2, BT_FN_VOID_UV4SI_UV4SI_UINTPTR_ULONGLONG) +B_DEF (s390_vsceg, vec_scatter_elementv2di_DI,0, B_VX, O4_U1, BT_FN_VOID_UV2DI_UV2DI_ULONGLONGPTR_ULONGLONG) /* First two operands are swapped in s390-c.cc */ OB_DEF (s390_vec_sel, s390_vec_sel_b8_a, s390_vec_sel_dbl_b, B_VX, BT_FN_OV4SI_OV4SI_OV4SI_OV4SI) diff --git a/gcc/config/s390/s390-c.cc b/gcc/config/s390/s390-c.cc index db9a88ee8054..3aa27c9034c0 100644 --- a/gcc/config/s390/s390-c.cc +++ b/gcc/config/s390/s390-c.cc @@ -420,10 +420,8 @@ s390_cpu_cpp_builtins (cpp_reader *pfile) cpp_assert (pfile, "cpu=s390"); cpp_assert (pfile, "machine=s390"); cpp_define (pfile, "__s390__"); - if (TARGET_ZARCH) - cpp_define (pfile, "__zarch__"); - if (TARGET_64BIT) - cpp_define (pfile, "__s390x__"); + cpp_define (pfile, "__zarch__"); + cpp_define (pfile, "__s390x__"); if (TARGET_LONG_DOUBLE_128) cpp_define (pfile, "__LONG_DOUBLE_128__"); cl_target_option_save (&opts, &global_options, &global_options_set); diff --git a/gcc/config/s390/s390-d.cc b/gcc/config/s390/s390-d.cc index 00bee9dd260a..ac9abedce641 100644 --- a/gcc/config/s390/s390-d.cc +++ b/gcc/config/s390/s390-d.cc @@ -30,13 +30,8 @@ along with GCC; see the file COPYING3. If not see void s390_d_target_versions (void) { - if (TARGET_64BIT) - { - d_add_builtin_version ("S390X"); - d_add_builtin_version ("SystemZ"); - } - else - d_add_builtin_version ("S390"); + d_add_builtin_version ("S390X"); + d_add_builtin_version ("SystemZ"); if (TARGET_SOFT_FLOAT) d_add_builtin_version ("D_SoftFloat"); diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index d57499a48e60..4ec9a53f7d76 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -398,11 +398,9 @@ struct s390_address #define cfun_frame_layout (cfun->machine->frame_layout) #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) -#define cfun_save_arg_fprs_p (!!(TARGET_64BIT \ - ? cfun_frame_layout.fpr_bitmap & 0x0f \ - : cfun_frame_layout.fpr_bitmap & 0x03)) +#define cfun_save_arg_fprs_p (!!(cfun_frame_layout.fpr_bitmap & 0x0f)) #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ - cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG) + cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD) #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \ (1 << (REGNO - FPR0_REGNUM))) #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \ @@ -412,7 +410,7 @@ struct s390_address /* Number of GPRs and FPRs used for argument passing. */ #define GP_ARG_NUM_REG 5 -#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2) +#define FP_ARG_NUM_REG 4 #define VEC_ARG_NUM_REG 8 /* Return TRUE if GPR REGNO is supposed to be restored in the function @@ -713,10 +711,7 @@ s390_init_builtins (void) uint64_t data type. What we want is c_uint64_type_node from c-common.cc. But since backend code is not supposed to interface with the frontend we recreate it here. */ - if (TARGET_64BIT) - c_uint64_type_node = long_unsigned_type_node; - else - c_uint64_type_node = long_long_unsigned_type_node; + c_uint64_type_node = long_unsigned_type_node; #undef DEF_TYPE #define DEF_TYPE(INDEX, NODE, CONST_P) \ @@ -1358,34 +1353,29 @@ s390_got_symbol (void) static scalar_int_mode s390_libgcc_cmp_return_mode (void) { - return TARGET_64BIT ? DImode : SImode; + return DImode; } static scalar_int_mode s390_libgcc_shift_count_mode (void) { - return TARGET_64BIT ? DImode : SImode; + return DImode; } static scalar_int_mode s390_unwind_word_mode (void) { - return TARGET_64BIT ? DImode : SImode; + return DImode; } /* Return true if the back end supports mode MODE. */ static bool s390_scalar_mode_supported_p (scalar_mode mode) { - /* In contrast to the default implementation reject TImode constants on 31bit - TARGET_ZARCH for ABI compliance. */ - if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode) - return false; - if (DECIMAL_FLOAT_MODE_P (mode)) return default_decimal_float_supported_p (); - if (TARGET_64BIT && TARGET_Z10 && mode == HFmode) + if (TARGET_Z10 && mode == HFmode) return true; return default_scalar_mode_supported_p (mode); @@ -1665,8 +1655,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))) || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os") - /* Avoid INT32_MIN on 32 bit. */ - && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1)))) + && INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))) { if (INTVAL (XEXP((op0), 1)) < 0) return CCANmode; @@ -3598,8 +3587,7 @@ s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend) if (GET_CODE (addr) == SYMBOL_REF || (GET_CODE (addr) == UNSPEC - && (XINT (addr, 1) == UNSPEC_GOTENT - || XINT (addr, 1) == UNSPEC_PLT31))) + && XINT (addr, 1) == UNSPEC_GOTENT)) { if (symref) *symref = addr; @@ -4173,30 +4161,13 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code, { rtx left = XEXP (x, 0); rtx right = XEXP (x, 1); - if (TARGET_ZARCH) - { - if (GET_CODE (right) == CONST_INT - && CONST_OK_FOR_K (INTVAL (right))) - *total = s390_cost->mghi; - else if (GET_CODE (left) == SIGN_EXTEND) - *total = s390_cost->msgf; - else - *total = s390_cost->msg; /* msgr, msg */ - } - else /* TARGET_31BIT */ - { - if (GET_CODE (left) == SIGN_EXTEND - && GET_CODE (right) == SIGN_EXTEND) - /* mulsidi case: mr, m */ - *total = s390_cost->m; - else if (GET_CODE (left) == ZERO_EXTEND - && GET_CODE (right) == ZERO_EXTEND) - /* umulsidi case: ml, mlr */ - *total = s390_cost->ml; - else - /* Complex calculation is required. */ - *total = COSTS_N_INSNS (40); - } + if (GET_CODE (right) == CONST_INT + && CONST_OK_FOR_K (INTVAL (right))) + *total = s390_cost->mghi; + else if (GET_CODE (left) == SIGN_EXTEND) + *total = s390_cost->msgf; + else + *total = s390_cost->msg; /* msgr, msg */ break; } case E_SFmode: @@ -4255,10 +4226,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code, { rtx right = XEXP (x, 1); if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ - if (TARGET_ZARCH) - *total = s390_cost->dsgfr; - else - *total = s390_cost->dr; + *total = s390_cost->dsgfr; else /* 64 by 64 bit division */ *total = s390_cost->dsgr; } @@ -4421,7 +4389,6 @@ tls_symbolic_operand (rtx op) void s390_split_access_reg (rtx reg, rtx *lo, rtx *hi) { - gcc_assert (TARGET_64BIT); gcc_assert (ACCESS_REG_P (reg)); gcc_assert (GET_MODE (reg) == DImode); gcc_assert (!(REGNO (reg) & 1)); @@ -4653,16 +4620,15 @@ legitimate_reload_constant_p (rtx op) return true; /* Accept lliXX operands. */ - if (TARGET_ZARCH - && GET_CODE (op) == CONST_INT - && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) - && s390_single_part (op, word_mode, HImode, 0) >= 0) + if (GET_CODE (op) == CONST_INT + && trunc_int_for_mode (INTVAL (op), DImode) == INTVAL (op) + && s390_single_part (op, DImode, HImode, 0) >= 0) return true; if (TARGET_EXTIMM && GET_CODE (op) == CONST_INT - && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) - && s390_single_part (op, word_mode, SImode, 0) >= 0) + && trunc_int_for_mode (INTVAL (op), DImode) == INTVAL (op) + && s390_single_part (op, DImode, SImode, 0) >= 0) return true; /* Accept larl operands. */ @@ -4678,11 +4644,10 @@ legitimate_reload_constant_p (rtx op) /* Accept double-word operands that can be split. */ if (GET_CODE (op) == CONST_WIDE_INT || (GET_CODE (op) == CONST_INT - && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))) + && trunc_int_for_mode (INTVAL (op), DImode) != INTVAL (op))) { - machine_mode dword_mode = word_mode == SImode ? DImode : TImode; - rtx hi = operand_subword (op, 0, 0, dword_mode); - rtx lo = operand_subword (op, 1, 0, dword_mode); + rtx hi = operand_subword (op, 0, 0, TImode); + rtx lo = operand_subword (op, 1, 0, TImode); return legitimate_reload_constant_p (hi) && legitimate_reload_constant_p (lo); } @@ -4848,7 +4813,7 @@ s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment) } if (GET_CODE (symref) == UNSPEC - && alignment <= UNITS_PER_LONG) + && alignment <= UNITS_PER_WORD) return true; return false; @@ -4974,13 +4939,9 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, && s390_class_max_nregs (FP_REGS, mode) == 1))) { if (in_p) - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_la_in : - CODE_FOR_reloadsi_la_in); + sri->icode = CODE_FOR_reloaddi_la_in; else - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_la_out : - CODE_FOR_reloadsi_la_out); + sri->icode = CODE_FOR_reloaddi_la_out; } } @@ -4996,8 +4957,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, && mode == Pmode && (!SYMBOL_REF_P (symref) || !SYMBOL_FLAG_NOTALIGN2_P (symref)) && (offset & 1) == 1) - sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10 - : CODE_FOR_reloadsi_larl_odd_addend_z10); + sri->icode = CODE_FOR_reloaddi_larl_odd_addend_z10; /* Handle all the (mem (symref)) accesses we cannot use the z10 instructions for. */ @@ -5011,12 +4971,8 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, { #define __SECONDARY_RELOAD_CASE(M,m) \ case E_##M##mode: \ - if (TARGET_64BIT) \ - sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \ - CODE_FOR_reload##m##di_tomem_z10; \ - else \ - sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \ - CODE_FOR_reload##m##si_tomem_z10; \ + sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \ + CODE_FOR_reload##m##di_tomem_z10; \ break; switch (GET_MODE (x)) @@ -5070,8 +5026,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, /* LRA can deal with transformation of plus op very well -- so we don't need to prompt LRA in this case. */ if (! lra_in_progress && in_p && s390_plus_operand (x, mode)) - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus); + sri->icode = CODE_FOR_reloaddi_plus; /* Performing a multiword move from or to memory we have to make sure the second chunk in memory is addressable without causing a displacement @@ -5095,13 +5050,9 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, && s390_class_max_nregs (FP_REGS, mode) > 1)) { if (in_p) - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_la_in : - CODE_FOR_reloadsi_la_in); + sri->icode = CODE_FOR_reloaddi_la_in; else - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_la_out : - CODE_FOR_reloadsi_la_out); + sri->icode = CODE_FOR_reloaddi_la_out; } } @@ -5109,9 +5060,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, copied to r0 compiling with -fPIC. In other cases the target register might be used as temporary (see legitimize_pic_address). */ if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS) - sri->icode = (TARGET_64BIT ? - CODE_FOR_reloaddi_PIC_addr : - CODE_FOR_reloadsi_PIC_addr); + sri->icode = CODE_FOR_reloaddi_PIC_addr; /* Either scratch or no register needed. */ return NO_REGS; @@ -5122,9 +5071,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, We need secondary memory to move data between GPRs and FPRs. - With DFP the ldgr lgdr instructions are available. Due to the - different alignment we cannot use them for SFmode. For 31 bit a - 64 bit value in GPR would be a register pair so here we still - need to go via memory. + different alignment we cannot use them for SFmode. - With z13 we can do the SF/SImode moves with vlgvf. Due to the overlapping of FPRs and VRs we still disallow TF/TD modes to be @@ -5141,7 +5088,7 @@ s390_secondary_memory_needed (machine_mode mode, realized via ldgr/lgdr in conjunction with shifts in order satisfy alignment requirements, or via vector loads. Thus, there is no secondary memory needed. */ - if (TARGET_64BIT && TARGET_Z10 && GET_MODE_SIZE (mode) == 2 + if (TARGET_Z10 && GET_MODE_SIZE (mode) == 2 && ((reg_classes_intersect_p (class1, VEC_REGS) && reg_classes_intersect_p (class2, GENERAL_REGS)) || (reg_classes_intersect_p (class2, VEC_REGS) @@ -5151,8 +5098,7 @@ s390_secondary_memory_needed (machine_mode mode, && reg_classes_intersect_p (class2, GENERAL_REGS)) || (reg_classes_intersect_p (class1, GENERAL_REGS) && reg_classes_intersect_p (class2, VEC_REGS))) - && (TARGET_TPF || !TARGET_DFP || !TARGET_64BIT - || GET_MODE_SIZE (mode) != 8) + && (TARGET_TPF || !TARGET_DFP || GET_MODE_SIZE (mode) != 8) && (!TARGET_VX || (SCALAR_FLOAT_MODE_P (mode) && GET_MODE_SIZE (mode) > 8))); } @@ -5282,9 +5228,7 @@ s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict, return true; } -/* Return true if OP is a valid operand for the LA instruction. - In 31-bit, we need to prove that the result is used as an - address, as LA performs only a 31-bit addition. */ +/* Return true if OP is a valid operand for the LA instruction. */ bool legitimate_la_operand_p (rtx op) @@ -5293,7 +5237,7 @@ legitimate_la_operand_p (rtx op) if (!s390_decompose_address (op, &addr)) return false; - return (TARGET_64BIT || addr.pointer); + return true; } /* Return true if it is valid *and* preferable to use LA to @@ -5321,9 +5265,6 @@ preferred_la_operand_p (rtx op1, rtx op2) if (addr.indx && s390_tune >= PROCESSOR_2817_Z196) return false; - if (!TARGET_64BIT && !addr.pointer) - return false; - if (addr.pointer) return true; @@ -5341,10 +5282,7 @@ preferred_la_operand_p (rtx op1, rtx op2) void s390_load_address (rtx dst, rtx src) { - if (TARGET_64BIT) - emit_move_insn (dst, src); - else - emit_insn (gen_force_la_31 (dst, src)); + emit_move_insn (dst, src); } /* Return true if it ok to use SYMBOL_REF in a relative address. */ @@ -5405,9 +5343,7 @@ legitimize_pic_address (rtx orig, rtx reg) if ((GET_CODE (addr) == LABEL_REF || (SYMBOL_REF_P (addr) && s390_rel_address_ok_p (addr)) - || (GET_CODE (addr) == UNSPEC && - (XINT (addr, 1) == UNSPEC_GOTENT - || XINT (addr, 1) == UNSPEC_PLT31))) + || (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_GOTENT)) && GET_CODE (addend) == CONST_INT) { /* This can be locally addressed. */ @@ -5504,8 +5440,7 @@ legitimize_pic_address (rtx orig, rtx reg) else if (flag_pic == 1) { /* Assume GOT offset is a valid displacement operand (< 4k - or < 512k with z990). This is handled the same way in - both 31- and 64-bit code (@GOT). + or < 512k with z990). lg <target>, sym@GOT(r12) */ if (reload_in_progress || reload_completed) @@ -5566,12 +5501,6 @@ legitimize_pic_address (rtx orig, rtx reg) gcc_unreachable (); break; - /* For @PLT larl is used. This is handled like local - symbol refs. */ - case UNSPEC_PLT31: - gcc_unreachable (); - break; - /* Everything else cannot happen. */ default: gcc_unreachable (); @@ -5611,7 +5540,7 @@ s390_get_thread_pointer (void) { rtx tp = gen_reg_rtx (Pmode); - emit_insn (gen_get_thread_pointer (Pmode, tp)); + emit_insn (gen_get_thread_pointerdi (tp)); mark_reg_pointer (tp, BITS_PER_WORD); @@ -5715,8 +5644,7 @@ legitimize_tls_address (rtx addr, rtx reg) case TLS_MODEL_INITIAL_EXEC: if (flag_pic == 1) { - /* Assume GOT offset < 4k. This is handled the same way - in both 31- and 64-bit code. */ + /* Assume GOT offset < 4k. */ if (reload_in_progress || reload_completed) df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); @@ -6329,12 +6257,8 @@ s390_expand_setmem (rtx dst, rtx len, rtx val, rtx min_len_rtx, rtx max_len_rtx) else if (TARGET_MVCLE) { val = force_not_mem (convert_modes (Pmode, QImode, val, 1)); - if (TARGET_64BIT) - emit_insn (gen_setmem_long_di (dst, convert_to_mode (Pmode, len, 1), - val)); - else - emit_insn (gen_setmem_long_si (dst, convert_to_mode (Pmode, len, 1), - val)); + emit_insn (gen_setmem_long_di (dst, convert_to_mode (Pmode, len, 1), + val)); } /* Non-constant length and no loop required. */ @@ -6762,12 +6686,8 @@ s390_expand_vec_strlen (rtx target, rtx string, rtx alignment) s390_load_address (highest_index_to_load_reg, gen_rtx_PLUS (Pmode, highest_index_to_load_reg, const1_rtx)); - if (TARGET_64BIT) - emit_insn (gen_movdicc (str_idx_reg, cond, - highest_index_to_load_reg, str_idx_reg)); - else - emit_insn (gen_movsicc (str_idx_reg, cond, - highest_index_to_load_reg, str_idx_reg)); + emit_insn (gen_movdicc (str_idx_reg, cond, + highest_index_to_load_reg, str_idx_reg)); add_reg_br_prob_note (s390_emit_jump (is_aligned_label, cond), profile_probability::very_unlikely ()); @@ -7108,8 +7028,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) /* Generate INSERT IMMEDIATE (IILL et al). */ /* (set (ze (reg)) (const_int)). */ - if (TARGET_ZARCH - && register_operand (dest, word_mode) + if (register_operand (dest, DImode) && (bitpos % 16) == 0 && (bitsize % 16) == 0 && const_int_operand (src, VOIDmode)) @@ -7129,7 +7048,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) putsize = GET_MODE_BITSIZE (putmode); regpos -= putsize; - emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, + emit_move_insn (gen_rtx_ZERO_EXTRACT (DImode, dest, GEN_INT (putsize), GEN_INT (regpos)), gen_int_mode (val, putmode)); @@ -7147,7 +7066,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) if (bitpos == 0 && (bitsize % BITS_PER_UNIT) == 0 && MEM_P (dest) - && (register_operand (src, word_mode) + && (register_operand (src, DImode) || const_int_operand (src, VOIDmode))) { /* Emit standard pattern if possible. */ @@ -7162,7 +7081,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) else if (const_int_operand (src, VOIDmode)) { int size = bitsize / BITS_PER_UNIT; - rtx src_mem = adjust_address (force_const_mem (word_mode, src), + rtx src_mem = adjust_address (force_const_mem (DImode, src), BLKmode, UNITS_PER_WORD - size); @@ -7174,10 +7093,10 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) } /* (set (ze (mem)) (reg)). */ - else if (register_operand (src, word_mode)) + else if (register_operand (src, DImode)) { if (bitsize <= 32) - emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1, + emit_move_insn (gen_rtx_ZERO_EXTRACT (DImode, dest, op1, const0_rtx), src); else { @@ -7188,10 +7107,10 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) emit_move_insn (adjust_address (dest, SImode, size), gen_lowpart (SImode, src)); set_mem_size (dest, size); - emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, + emit_move_insn (gen_rtx_ZERO_EXTRACT (DImode, dest, GEN_INT (stcmh_width), const0_rtx), - gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32))); + gen_rtx_LSHIFTRT (DImode, src, GEN_INT (32))); } return true; } @@ -8467,7 +8386,6 @@ s390_dwarf_frame_reg_mode (int regno) { machine_mode save_mode = default_dwarf_frame_reg_mode (regno); - /* Make sure not to return DImode for any GPR with -m31 -mzarch. */ if (GENERAL_REGNO_P (regno)) save_mode = Pmode; @@ -8506,7 +8424,7 @@ s390_mangle_type (const_tree type) static bool s390_libgcc_floating_mode_supported_p (scalar_float_mode mode) { - return (TARGET_64BIT && TARGET_Z10 && mode == HFmode) + return (TARGET_Z10 && mode == HFmode) || default_libgcc_floating_mode_supported_p (mode); } @@ -8562,8 +8480,7 @@ s390_delegitimize_address (rtx orig_x) y = XEXP (x, 0); if (GET_CODE (y) == UNSPEC - && (XINT (y, 1) == UNSPEC_GOTENT - || XINT (y, 1) == UNSPEC_PLT31)) + && XINT (y, 1) == UNSPEC_GOTENT) return XVECEXP (y, 0, 0); else return orig_x; @@ -8593,8 +8510,7 @@ s390_delegitimize_address (rtx orig_x) y = XEXP (x, 0); if (GET_CODE (y) == UNSPEC - && (XINT (y, 1) == UNSPEC_GOTENT - || XINT (y, 1) == UNSPEC_PLT31)) + && XINT (y, 1) == UNSPEC_GOTENT) y = XVECEXP (y, 0, 0); else return orig_x; @@ -8701,8 +8617,7 @@ s390_function_num_hotpatch_hw (tree decl, static void s390_asm_output_machine_for_arch (FILE *asm_out_file) { - fprintf (asm_out_file, "\t.machinemode %s\n", - (TARGET_ZARCH) ? "zarch" : "esa"); + fprintf (asm_out_file, "\t.machinemode zarch\n"); fprintf (asm_out_file, "\t.machine \"%s", processor_table[s390_arch].binutils_name); if (S390_USE_ARCHITECTURE_MODIFIERS) @@ -8779,10 +8694,9 @@ s390_asm_output_function_label (FILE *out_file, const char *fname, /* Note: The function label must be aligned so that (a) the bytes of the following nop do not cross a cacheline boundary, and (b) a jump address - (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be - stored directly before the label without crossing a cacheline - boundary. All this is necessary to make sure the trampoline code can - be changed atomically. + (eight bytes) can be stored directly before the label without crossing + a cacheline boundary. All this is necessary to make sure the + trampoline code can be changed atomically. This alignment is done automatically using the FOUNCTION_BOUNDARY, but if there are NOPs before the function label, the alignment is placed before them. So it is necessary to duplicate the alignment after the @@ -8847,10 +8761,6 @@ s390_output_addr_const_extra (FILE *file, rtx x) output_addr_const (file, XVECEXP (x, 0, 0)); fprintf (file, "@GOTOFF"); return true; - case UNSPEC_PLT31: - output_addr_const (file, XVECEXP (x, 0, 0)); - fprintf (file, "@PLT"); - return true; case UNSPEC_PLTOFF: output_addr_const (file, XVECEXP (x, 0, 0)); fprintf (file, "@PLTOFF"); @@ -10570,9 +10480,9 @@ s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) return get_hard_reg_initial_val (Pmode, RETURN_REGNUM); if (TARGET_PACKED_STACK) - offset = -2 * UNITS_PER_LONG; + offset = -2 * UNITS_PER_WORD; else - offset = RETURN_REGNUM * UNITS_PER_LONG; + offset = RETURN_REGNUM * UNITS_PER_WORD; addr = plus_constant (Pmode, frame, offset); addr = memory_address (Pmode, addr); @@ -10591,7 +10501,7 @@ s390_back_chain_rtx (void) if (TARGET_PACKED_STACK) chain = plus_constant (Pmode, stack_pointer_rtx, - STACK_POINTER_OFFSET - UNITS_PER_LONG); + STACK_POINTER_OFFSET - UNITS_PER_WORD); else chain = stack_pointer_rtx; @@ -10743,31 +10653,18 @@ s390_frame_area (int *area_bottom, int *area_top) if (cfun_frame_layout.first_restore_gpr != -1) { b = (cfun_frame_layout.gprs_offset - + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG); + + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD); t = b + (cfun_frame_layout.last_restore_gpr - - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG; + - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD; } - if (TARGET_64BIT && cfun_save_high_fprs_p) + if (cfun_save_high_fprs_p) { b = MIN (b, cfun_frame_layout.f8_offset); t = MAX (t, (cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8)); } - if (!TARGET_64BIT) - { - if (cfun_fpr_save_p (FPR4_REGNUM)) - { - b = MIN (b, cfun_frame_layout.f4_offset); - t = MAX (t, cfun_frame_layout.f4_offset + 8); - } - if (cfun_fpr_save_p (FPR6_REGNUM)) - { - b = MIN (b, cfun_frame_layout.f4_offset + 8); - t = MAX (t, cfun_frame_layout.f4_offset + 16); - } - } *area_bottom = b; *area_top = t; } @@ -10827,8 +10724,7 @@ s390_register_info_arg_fpr () int min_preserve_fpr = INT_MAX, max_preserve_fpr = -1; int min_fpr, max_fpr; - /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and - f0-f4 for 64 bit. */ + /* Save the FP argument regs f0-f4 for stdarg. */ if (cfun->stdarg && TARGET_HARD_FLOAT && cfun->va_list_fpr_size @@ -11107,7 +11003,7 @@ s390_frame_info (void) cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr; /* The va_arg builtin uses a constant distance of 16 * - UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area + UNITS_PER_WORD (r0-r15) to reach the FPRs from the reg_save_area pointer. So even if we are going to save the stack pointer in an FPR we need the stack space in order to keep the offsets correct. */ @@ -11120,26 +11016,23 @@ s390_frame_info (void) } cfun_frame_layout.frame_size = get_frame_size (); - if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000) - fatal_error (input_location, - "total size of local variables exceeds architecture limit"); if (!TARGET_PACKED_STACK) { /* Fixed stack layout. */ cfun_frame_layout.backchain_offset = 0; - cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG; + cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD; cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot - * UNITS_PER_LONG); + * UNITS_PER_WORD); } else if (TARGET_BACKCHAIN) { /* Kernel stack layout - packed stack, backchain, no float */ gcc_assert (TARGET_SOFT_FLOAT); cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET - - UNITS_PER_LONG); + - UNITS_PER_WORD); /* The distance between the backchain and the return address save slot must not change. So we always need a slot for the @@ -11162,7 +11055,7 @@ s390_frame_info (void) /* Packed stack layout without backchain. */ /* With stdarg FPRs need their dedicated slots. */ - num_fprs = (TARGET_64BIT && cfun->stdarg ? 2 + num_fprs = (cfun->stdarg ? 2 : (cfun_fpr_save_p (FPR4_REGNUM) + cfun_fpr_save_p (FPR6_REGNUM))); cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs; @@ -11211,9 +11104,7 @@ s390_frame_info (void) cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset; - /* If under 31 bit an odd number of gprs has to be saved we have to - adjust the frame size to sustain 8 byte alignment of stack - frames. */ + /* Adjust frame size to sustain 8 byte alignment of stack frames. */ cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size + STACK_BOUNDARY / BITS_PER_UNIT - 1) & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); @@ -11490,11 +11381,7 @@ s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* fallthrough */ case GENERAL_REGS: if (REGNO_PAIR_OK (regno, mode)) - { - if (TARGET_ZARCH - || (mode != TFmode && mode != TCmode && mode != TDmode)) - return true; - } + return true; break; case CC_REGS: if (GET_MODE_CLASS (mode) == MODE_CC) @@ -11563,32 +11450,16 @@ s390_hard_regno_scratch_ok (unsigned int regno) return true; } -/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. When generating - code that runs in z/Architecture mode, but conforms to the 31-bit - ABI, GPRs can hold 8 bytes; the ABI guarantees only that the lower 4 - bytes are saved across calls, however. */ +/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */ static bool s390_hard_regno_call_part_clobbered (unsigned int, unsigned int regno, machine_mode mode) { - /* For r12 we know that the only bits we actually care about are - preserved across function calls. Since r12 is a fixed reg all - accesses to r12 are generated by the backend. - - This workaround is necessary until gcse implements proper - tracking of partially clobbered registers. */ - if (!TARGET_64BIT - && TARGET_ZARCH - && GET_MODE_SIZE (mode) > 4 - && (!flag_pic || regno != PIC_OFFSET_TABLE_REGNUM) - && ((regno >= 6 && regno <= 15) || regno == 32)) - return true; - if (TARGET_VX && GET_MODE_SIZE (mode) > 8 - && (((TARGET_64BIT && regno >= 24 && regno <= 31)) - || (!TARGET_64BIT && (regno == 18 || regno == 19)))) + && regno >= 24 + && regno <= 31) return true; return false; @@ -11789,7 +11660,7 @@ s390_initial_elimination_offset (int from, int to) reside. */ offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset + (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) * - UNITS_PER_LONG); + UNITS_PER_WORD); break; case BASE_REGNUM: @@ -11864,10 +11735,7 @@ save_gprs (rtx base, int offset, int first, int last, rtx_insn *before = NULL) /* Special-case single register. */ if (first == last) { - if (TARGET_64BIT) - insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); - else - insn = gen_movsi (addr, gen_rtx_REG (Pmode, first)); + insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); if (!global_not_special_regno_p (first)) RTX_FRAME_RELATED_P (insn) = 1; @@ -11935,7 +11803,7 @@ save_gprs (rtx base, int offset, int first, int last, rtx_insn *before = NULL) { rtx reg = gen_rtx_REG (Pmode, regno); rtx reg_addr = plus_constant (Pmode, base, - offset + (regno - first) * UNITS_PER_LONG); + offset + (regno - first) * UNITS_PER_WORD); if (!s390_restore_gpr_p (regno)) add_reg_note (insn, REG_CFA_NO_RESTORE, reg); add_reg_note (insn, REG_CFA_OFFSET, @@ -11955,16 +11823,12 @@ save_gprs (rtx base, int offset, int first, int last, rtx_insn *before = NULL) goto emit; addr = plus_constant (Pmode, base, - offset + (start - first) * UNITS_PER_LONG); + offset + (start - first) * UNITS_PER_WORD); if (start == last) { - if (TARGET_64BIT) - note = gen_movdi (gen_rtx_MEM (Pmode, addr), - gen_rtx_REG (Pmode, start)); - else - note = gen_movsi (gen_rtx_MEM (Pmode, addr), - gen_rtx_REG (Pmode, start)); + note = gen_movdi (gen_rtx_MEM (Pmode, addr), + gen_rtx_REG (Pmode, start)); note = PATTERN (note); add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); @@ -12013,10 +11877,7 @@ restore_gprs (rtx base, int offset, int first, int last) /* Special-case single register. */ if (first == last) { - if (TARGET_64BIT) - insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); - else - insn = gen_movsi (gen_rtx_REG (Pmode, first), addr); + insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); RTX_FRAME_RELATED_P (insn) = 1; return insn; @@ -12058,9 +11919,9 @@ s390_emit_stack_tie (void) { rtx mem = gen_frame_mem (BLKmode, stack_pointer_rtx); if (frame_pointer_needed) - emit_insn (gen_stack_tie (Pmode, mem, hard_frame_pointer_rtx)); + emit_insn (gen_stack_tiedi (mem, hard_frame_pointer_rtx)); else - emit_insn (gen_stack_tie (Pmode, mem, stack_pointer_rtx)); + emit_insn (gen_stack_tiedi (mem, stack_pointer_rtx)); } /* Copy GPRS into FPR save slots. */ @@ -12267,7 +12128,7 @@ s390_prologue_plus_offset (rtx target, rtx reg, rtx offset, bool frame_related_p static void s390_emit_stack_probe (rtx addr) { - rtx mem = gen_rtx_MEM (word_mode, addr); + rtx mem = gen_rtx_MEM (DImode, addr); MEM_VOLATILE_P (mem) = 1; emit_insn (gen_probe_stack (mem)); } @@ -12298,7 +12159,7 @@ allocate_stack_space (rtx size, HOST_WIDE_INT last_probe_offset, dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true); else { - rtx offset = GEN_INT (probe_interval - UNITS_PER_LONG); + rtx offset = GEN_INT (probe_interval - UNITS_PER_WORD); HOST_WIDE_INT rounded_size = -INTVAL (size) & -probe_interval; HOST_WIDE_INT num_probes = rounded_size / probe_interval; HOST_WIDE_INT residual = -INTVAL (size) - rounded_size; @@ -12364,7 +12225,7 @@ allocate_stack_space (rtx size, HOST_WIDE_INT last_probe_offset, s390_emit_stack_probe (gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (residual - - UNITS_PER_LONG))); + - UNITS_PER_WORD))); return temp_reg_clobbered_p; } @@ -12412,7 +12273,7 @@ s390_emit_prologue (void) = 1 << param_stack_clash_protection_probe_interval; HOST_WIDE_INT last_probe_offset = (TARGET_BACKCHAIN - ? (TARGET_PACKED_STACK ? STACK_POINTER_OFFSET - UNITS_PER_LONG : 0) + ? (TARGET_PACKED_STACK ? STACK_POINTER_OFFSET - UNITS_PER_WORD : 0) : probe_interval - (STACK_BOUNDARY / UNITS_PER_WORD)); s390_save_gprs_to_fprs (); @@ -12422,7 +12283,7 @@ s390_emit_prologue (void) { save_gprs (stack_pointer_rtx, cfun_frame_layout.gprs_offset + - UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr + UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr - cfun_frame_layout.first_save_gpr_slot), cfun_frame_layout.first_save_gpr, cfun_frame_layout.last_save_gpr); @@ -12431,7 +12292,7 @@ s390_emit_prologue (void) then LAST_PROBE_OFFSET can move even closer to sp. */ last_probe_offset = (cfun_frame_layout.gprs_offset + - UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr + UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr - cfun_frame_layout.first_save_gpr_slot)); } @@ -12552,14 +12413,9 @@ s390_emit_prologue (void) rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx, GEN_INT (stack_check_mask)); - if (TARGET_64BIT) - emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, - t, const0_rtx), - t, const0_rtx, const0_rtx)); - else - emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, - t, const0_rtx), - t, const0_rtx, const0_rtx)); + emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, + t, const0_rtx), + t, const0_rtx, const0_rtx)); } } } @@ -12775,31 +12631,10 @@ s390_emit_epilogue (bool sibcall) /* Restore call saved fprs. */ - if (TARGET_64BIT) - { - if (cfun_save_high_fprs_p) - { - next_offset = cfun_frame_layout.f8_offset; - for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) - { - if (cfun_fpr_save_p (i)) - { - restore_fpr (frame_pointer, - offset + next_offset, i); - cfa_restores - = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (DFmode, i), cfa_restores); - next_offset += 8; - } - } - } - - } - else + if (cfun_save_high_fprs_p) { - next_offset = cfun_frame_layout.f4_offset; - /* f4, f6 */ - for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++) + next_offset = cfun_frame_layout.f8_offset; + for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) { if (cfun_fpr_save_p (i)) { @@ -12810,10 +12645,7 @@ s390_emit_epilogue (bool sibcall) gen_rtx_REG (DFmode, i), cfa_restores); next_offset += 8; } - else if (!TARGET_PACKED_STACK) - next_offset += 8; } - } /* Restore call saved gprs. */ @@ -12835,7 +12667,7 @@ s390_emit_epilogue (bool sibcall) addr = plus_constant (Pmode, frame_pointer, offset + cfun_frame_layout.gprs_offset + (i - cfun_frame_layout.first_save_gpr_slot) - * UNITS_PER_LONG); + * UNITS_PER_WORD); addr = gen_rtx_MEM (Pmode, addr); set_mem_alias_set (addr, get_frame_alias_set ()); emit_move_insn (addr, gen_rtx_REG (Pmode, i)); @@ -12875,7 +12707,7 @@ s390_emit_epilogue (bool sibcall) offset + cfun_frame_layout.gprs_offset + (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) - * UNITS_PER_LONG); + * UNITS_PER_WORD); addr = gen_rtx_MEM (Pmode, addr); set_mem_alias_set (addr, get_frame_alias_set ()); emit_move_insn (return_reg, addr); @@ -12891,7 +12723,7 @@ s390_emit_epilogue (bool sibcall) offset + cfun_frame_layout.gprs_offset + (cfun_frame_layout.first_restore_gpr - cfun_frame_layout.first_save_gpr_slot) - * UNITS_PER_LONG, + * UNITS_PER_WORD, cfun_frame_layout.first_restore_gpr, cfun_frame_layout.last_restore_gpr); insn = emit_insn (insn); @@ -12956,25 +12788,13 @@ s390_output_split_stack_data (rtx parm_block, rtx call_done, switch_to_section (targetm.asm_out.function_rodata_section (current_function_decl, false)); - if (TARGET_64BIT) - output_asm_insn (".align\t8", NULL); - else - output_asm_insn (".align\t4", NULL); + output_asm_insn (".align\t8", NULL); (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (parm_block)); - if (TARGET_64BIT) - { - output_asm_insn (".quad\t%0", &frame_size); - output_asm_insn (".quad\t%0", &args_size); - output_asm_insn (".quad\t%1-%0", ops); - } - else - { - output_asm_insn (".long\t%0", &frame_size); - output_asm_insn (".long\t%0", &args_size); - output_asm_insn (".long\t%1-%0", ops); - } + output_asm_insn (".quad\t%0", &frame_size); + output_asm_insn (".quad\t%0", &args_size); + output_asm_insn (".quad\t%1-%0", ops); switch_to_section (current_function_section ()); } @@ -12988,7 +12808,7 @@ s390_expand_split_stack_prologue (void) rtx r1, guard, cc = NULL; rtx_insn *insn; /* Offset from thread pointer to __private_ss. */ - int psso = TARGET_64BIT ? 0x38 : 0x20; + int psso = 0x38; /* Pointer size in bytes. */ /* Frame size and argument size - the two parameters to __morestack. */ HOST_WIDE_INT frame_size = cfun_frame_layout.frame_size; @@ -13034,7 +12854,7 @@ s390_expand_split_stack_prologue (void) /* Get thread pointer. r1 is the only register we can always destroy - r0 could contain a static chain (and cannot be used to address memory anyway), r2-r6 can contain parameters, and r6-r15 are callee-saved. */ - emit_insn (gen_get_thread_pointer (Pmode, r1)); + emit_insn (gen_get_thread_pointerdi (r1)); /* Aim at __private_ss. */ guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, r1, psso)); @@ -13043,10 +12863,7 @@ s390_expand_split_stack_prologue (void) if (frame_size > SPLIT_STACK_AVAILABLE) { emit_move_insn (r1, guard); - if (TARGET_64BIT) - emit_insn (gen_adddi3 (r1, r1, GEN_INT (frame_size))); - else - emit_insn (gen_addsi3 (r1, r1, GEN_INT (frame_size))); + emit_insn (gen_adddi3 (r1, r1, GEN_INT (frame_size))); guard = r1; } @@ -13068,20 +12885,18 @@ s390_expand_split_stack_prologue (void) conventions: it preserves param/return/static chain registers for calling main function body, and looks for its own parameters at %r1. */ if (cc != NULL) - tmp = gen_split_stack_cond_call (Pmode, - morestack_ref, - parm_base, - call_done, - GEN_INT (frame_size), - GEN_INT (args_size), - cc); + tmp = gen_split_stack_cond_calldi (morestack_ref, + parm_base, + call_done, + GEN_INT (frame_size), + GEN_INT (args_size), + cc); else - tmp = gen_split_stack_call (Pmode, - morestack_ref, - parm_base, - call_done, - GEN_INT (frame_size), - GEN_INT (args_size)); + tmp = gen_split_stack_calldi (morestack_ref, + parm_base, + call_done, + GEN_INT (frame_size), + GEN_INT (args_size)); insn = emit_jump_insn (tmp); JUMP_LABEL (insn) = call_done; @@ -13159,13 +12974,6 @@ s390_can_use_return_insn (void) if (cfun_gpr_save_slot (i) != SAVE_SLOT_NONE) return false; - /* For 31 bit this is not covered by the frame_size check below - since f4, f6 are saved in the register save area without needing - additional stack space. */ - if (!TARGET_64BIT - && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM))) - return false; - if (cfun->machine->base_reg && !call_used_regs[REGNO (cfun->machine->base_reg)]) return false; @@ -13461,8 +13269,7 @@ s390_function_arg_advance (cumulative_args_t cum_v, } else if (s390_function_arg_integer (arg.mode, arg.type)) { - int size = s390_function_arg_size (arg.mode, arg.type); - cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG); + cum->gprs += 1; } else gcc_unreachable (); @@ -13478,9 +13285,8 @@ s390_function_arg_advance (cumulative_args_t cum_v, On S/390, we use general purpose registers 2 through 6 to pass integer, pointer, and certain structure arguments, and - floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit) - to pass floating point arguments. All remaining arguments - are pushed to the stack. */ + floating point registers 0, 2, 4, and 6 to pass floating point + arguments. All remaining arguments are pushed to the stack. */ static rtx s390_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) @@ -13508,26 +13314,10 @@ s390_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) } else if (s390_function_arg_integer (arg.mode, arg.type)) { - int size = s390_function_arg_size (arg.mode, arg.type); - int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; - - if (cum->gprs + n_gprs > GP_ARG_NUM_REG) + if (cum->gprs + 1 > GP_ARG_NUM_REG) return NULL_RTX; - else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG) + else return gen_rtx_REG (arg.mode, cum->gprs + 2); - else if (n_gprs == 2) - { - rtvec p = rtvec_alloc (2); - - RTVEC_ELT (p, 0) - = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2), - const0_rtx); - RTVEC_ELT (p, 1) - = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3), - GEN_INT (4)); - - return gen_rtx_PARALLEL (arg.mode, p); - } } /* After the real arguments, expand_call calls us once again with an @@ -13589,16 +13379,20 @@ s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED) /* Function arguments and return values are promoted to word size. */ static machine_mode -s390_promote_function_mode (const_tree type, machine_mode mode, - int *punsignedp, +s390_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, + machine_mode mode, + int *punsignedp ATTRIBUTE_UNUSED, const_tree fntype ATTRIBUTE_UNUSED, int for_return ATTRIBUTE_UNUSED) { if (INTEGRAL_MODE_P (mode) - && GET_MODE_SIZE (mode) < UNITS_PER_LONG) + && GET_MODE_SIZE (mode) < UNITS_PER_WORD) { +/* This is defined for TPF. */ +#ifdef POINTERS_EXTEND_UNSIGNED if (type != NULL_TREE && POINTER_TYPE_P (type)) *punsignedp = POINTERS_EXTEND_UNSIGNED; +#endif return Pmode; } @@ -13639,26 +13433,7 @@ s390_function_and_libcall_value (machine_mode mode, return gen_rtx_REG (mode, FIRST_VEC_ARG_REGNO); else if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode)) return gen_rtx_REG (mode, 16); - else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG - || UNITS_PER_LONG == UNITS_PER_WORD) - return gen_rtx_REG (mode, 2); - else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG) - { - /* This case is triggered when returning a 64 bit value with - -m31 -mzarch. Although the value would fit into a single - register it has to be forced into a 32 bit register pair in - order to match the ABI. */ - rtvec p = rtvec_alloc (2); - - RTVEC_ELT (p, 0) - = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx); - RTVEC_ELT (p, 1) - = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4)); - - return gen_rtx_PARALLEL (mode, p); - } - - gcc_unreachable (); + return gen_rtx_REG (mode, 2); } /* Define where to return a scalar return value of type RET_TYPE. */ @@ -13852,7 +13627,7 @@ s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG)) { t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); - t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG); + t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_WORD); t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); TREE_SIDE_EFFECTS (t) = 1; @@ -13896,7 +13671,7 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg; tree lab_false, lab_over = NULL_TREE; tree addr = create_tmp_var (ptr_type_node, "addr"); - bool left_align_p; /* How a value < UNITS_PER_LONG is aligned within + bool left_align_p; /* How a value < UNITS_PER_WORD is aligned within a stack slot. */ f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); @@ -13930,12 +13705,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, reg = gpr; n_reg = 1; - /* kernel stack layout on 31 bit: It is assumed here that no padding - will be added by s390_frame_info because for va_args always an even - number of gprs has to be saved r15-r2 = 14 regs. */ - sav_ofs = 2 * UNITS_PER_LONG; - sav_scale = UNITS_PER_LONG; - size = UNITS_PER_LONG; + sav_ofs = 2 * UNITS_PER_WORD; + sav_scale = UNITS_PER_WORD; + size = UNITS_PER_WORD; max_reg = GP_ARG_NUM_REG - n_reg; left_align_p = false; } @@ -13967,7 +13739,7 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, indirect_p = 0; reg = fpr; n_reg = 1; - sav_ofs = 16 * UNITS_PER_LONG; + sav_ofs = 16 * UNITS_PER_WORD; sav_scale = 8; max_reg = FP_ARG_NUM_REG - n_reg; left_align_p = false; @@ -13983,17 +13755,14 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, /* Otherwise into GP registers. */ indirect_p = 0; reg = gpr; - n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; + n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - /* kernel stack layout on 31 bit: It is assumed here that no padding - will be added by s390_frame_info because for va_args always an even - number of gprs has to be saved r15-r2 = 14 regs. */ - sav_ofs = 2 * UNITS_PER_LONG; + sav_ofs = 2 * UNITS_PER_WORD; - if (size < UNITS_PER_LONG) - sav_ofs += UNITS_PER_LONG - size; + if (size < UNITS_PER_WORD) + sav_ofs += UNITS_PER_WORD - size; - sav_scale = UNITS_PER_LONG; + sav_scale = UNITS_PER_WORD; max_reg = GP_ARG_NUM_REG - n_reg; left_align_p = false; } @@ -14037,15 +13806,15 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, /* ... Otherwise out of the overflow area. */ t = ovf; - if (size < UNITS_PER_LONG && !left_align_p) - t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size); + if (size < UNITS_PER_WORD && !left_align_p) + t = fold_build_pointer_plus_hwi (t, UNITS_PER_WORD - size); gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); gimplify_assign (addr, t, pre_p); - if (size < UNITS_PER_LONG && left_align_p) - t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG); + if (size < UNITS_PER_WORD && left_align_p) + t = fold_build_pointer_plus_hwi (t, UNITS_PER_WORD); else t = fold_build_pointer_plus_hwi (t, size); @@ -14187,20 +13956,10 @@ s390_asm_trampoline_template (FILE *file) op[0] = gen_rtx_REG (Pmode, 0); op[1] = gen_rtx_REG (Pmode, 1); - if (TARGET_64BIT) - { - output_asm_insn ("basr\t%1,0", op); /* 2 byte */ - output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */ - output_asm_insn ("br\t%1", op); /* 2 byte */ - ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); - } - else - { - output_asm_insn ("basr\t%1,0", op); /* 2 byte */ - output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */ - output_asm_insn ("br\t%1", op); /* 2 byte */ - ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8)); - } + output_asm_insn ("basr\t%1,0", op); /* 2 byte */ + output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */ + output_asm_insn ("br\t%1", op); /* 2 byte */ + ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); } /* Emit RTL insns to initialize the variable parts of a trampoline. @@ -14214,11 +13973,11 @@ s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) rtx mem; emit_block_move (m_tramp, assemble_trampoline_template (), - GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL); + GEN_INT (2 * UNITS_PER_WORD), BLOCK_OP_NORMAL); - mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG); + mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_WORD); emit_move_insn (mem, cxt); - mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG); + mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_WORD); emit_move_insn (mem, fnaddr); } @@ -14257,16 +14016,11 @@ s390_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); - op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG)); - op[3] = GEN_INT (UNITS_PER_LONG); + op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_WORD)); + op[3] = GEN_INT (UNITS_PER_WORD); op[2] = gen_rtx_SYMBOL_REF (Pmode, flag_fentry ? "__fentry__" : "_mcount"); SYMBOL_REF_FLAGS (op[2]) |= SYMBOL_FLAG_FUNCTION; - if (flag_pic && !TARGET_64BIT) - { - op[2] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[2]), UNSPEC_PLT31); - op[2] = gen_rtx_CONST (Pmode, op[2]); - } if (flag_record_mcount) fprintf (file, "1:\n"); @@ -14281,43 +14035,25 @@ s390_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) else output_asm_insn ("brasl\t0,%2%K2", op); } - else if (TARGET_64BIT) - { - if (flag_nop_mcount) - output_asm_nops ("-mnop-mcount", /* stg */ 3 + /* brasl */ 3 + - /* lg */ 3); - else - { - output_asm_insn ("stg\t%0,%1", op); - if (flag_dwarf2_cfi_asm) - output_asm_insn (".cfi_rel_offset\t%0,%3", op); - output_asm_insn ("brasl\t%0,%2%K2", op); - output_asm_insn ("lg\t%0,%1", op); - if (flag_dwarf2_cfi_asm) - output_asm_insn (".cfi_restore\t%0", op); - } - } + + if (flag_nop_mcount) + output_asm_nops ("-mnop-mcount", /* stg */ 3 + /* brasl */ 3 + + /* lg */ 3); else { - if (flag_nop_mcount) - output_asm_nops ("-mnop-mcount", /* st */ 2 + /* brasl */ 3 + - /* l */ 2); - else - { - output_asm_insn ("st\t%0,%1", op); - if (flag_dwarf2_cfi_asm) - output_asm_insn (".cfi_rel_offset\t%0,%3", op); - output_asm_insn ("brasl\t%0,%2%K2", op); - output_asm_insn ("l\t%0,%1", op); - if (flag_dwarf2_cfi_asm) - output_asm_insn (".cfi_restore\t%0", op); - } + output_asm_insn ("stg\t%0,%1", op); + if (flag_dwarf2_cfi_asm) + output_asm_insn (".cfi_rel_offset\t%0,%3", op); + output_asm_insn ("brasl\t%0,%2%K2", op); + output_asm_insn ("lg\t%0,%1", op); + if (flag_dwarf2_cfi_asm) + output_asm_insn (".cfi_restore\t%0", op); } if (flag_record_mcount) { fprintf (file, "\t.section __mcount_loc, \"a\",@progbits\n"); - fprintf (file, "\t.%s 1b\n", TARGET_64BIT ? "quad" : "long"); + fprintf (file, "\t.quad 1b\n"); fprintf (file, "\t.previous\n"); } } @@ -14386,7 +14122,6 @@ s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, { const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); rtx op[10]; - int nonlocal = 0; assemble_start_function (thunk, fnname); /* Make sure unwind info is emitted for the thunk if needed. */ @@ -14394,15 +14129,6 @@ s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, /* Operand 0 is the target function. */ op[0] = XEXP (DECL_RTL (function), 0); - if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0])) - { - nonlocal = 1; - if (!TARGET_64BIT) - { - op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]), UNSPEC_GOT); - op[0] = gen_rtx_CONST (Pmode, op[0]); - } - } /* Operand 1 is the 'this' pointer. */ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) @@ -14429,220 +14155,88 @@ s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, op[9] = NULL_RTX; /* Generate code. */ - if (TARGET_64BIT) - { - /* Setup literal pool pointer if required. */ - if ((!DISP_IN_RANGE (delta) - && !CONST_OK_FOR_K (delta) - && !CONST_OK_FOR_Os (delta)) - || (!DISP_IN_RANGE (vcall_offset) - && !CONST_OK_FOR_K (vcall_offset) - && !CONST_OK_FOR_Os (vcall_offset))) - { - op[5] = gen_label_rtx (); - output_asm_insn ("larl\t%4,%5", op); - } - - /* Add DELTA to this pointer. */ - if (delta) - { - if (CONST_OK_FOR_J (delta)) - output_asm_insn ("la\t%1,%2(%1)", op); - else if (DISP_IN_RANGE (delta)) - output_asm_insn ("lay\t%1,%2(%1)", op); - else if (CONST_OK_FOR_K (delta)) - output_asm_insn ("aghi\t%1,%2", op); - else if (CONST_OK_FOR_Os (delta)) - output_asm_insn ("agfi\t%1,%2", op); - else - { - op[6] = gen_label_rtx (); - output_asm_insn ("agf\t%1,%6-%5(%4)", op); - } - } - - /* Perform vcall adjustment. */ - if (vcall_offset) - { - if (DISP_IN_RANGE (vcall_offset)) - { - output_asm_insn ("lg\t%4,0(%1)", op); - output_asm_insn ("ag\t%1,%3(%4)", op); - } - else if (CONST_OK_FOR_K (vcall_offset)) - { - output_asm_insn ("lghi\t%4,%3", op); - output_asm_insn ("ag\t%4,0(%1)", op); - output_asm_insn ("ag\t%1,0(%4)", op); - } - else if (CONST_OK_FOR_Os (vcall_offset)) - { - output_asm_insn ("lgfi\t%4,%3", op); - output_asm_insn ("ag\t%4,0(%1)", op); - output_asm_insn ("ag\t%1,0(%4)", op); - } - else - { - op[7] = gen_label_rtx (); - output_asm_insn ("llgf\t%4,%7-%5(%4)", op); - output_asm_insn ("ag\t%4,0(%1)", op); - output_asm_insn ("ag\t%1,0(%4)", op); - } - } - - /* Jump to target. */ - output_asm_insn ("jg\t%0%K0", op); - - /* Output literal pool if required. */ - if (op[5]) - { - output_asm_insn (".align\t4", op); - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[5])); - } - if (op[6]) - { - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[6])); - output_asm_insn (".long\t%2", op); - } - if (op[7]) + /* Setup literal pool pointer if required. */ + if ((!DISP_IN_RANGE (delta) + && !CONST_OK_FOR_K (delta) + && !CONST_OK_FOR_Os (delta)) + || (!DISP_IN_RANGE (vcall_offset) + && !CONST_OK_FOR_K (vcall_offset) + && !CONST_OK_FOR_Os (vcall_offset))) + { + op[5] = gen_label_rtx (); + output_asm_insn ("larl\t%4,%5", op); + } + + /* Add DELTA to this pointer. */ + if (delta) + { + if (CONST_OK_FOR_J (delta)) + output_asm_insn ("la\t%1,%2(%1)", op); + else if (DISP_IN_RANGE (delta)) + output_asm_insn ("lay\t%1,%2(%1)", op); + else if (CONST_OK_FOR_K (delta)) + output_asm_insn ("aghi\t%1,%2", op); + else if (CONST_OK_FOR_Os (delta)) + output_asm_insn ("agfi\t%1,%2", op); + else { - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[7])); - output_asm_insn (".long\t%3", op); + op[6] = gen_label_rtx (); + output_asm_insn ("agf\t%1,%6-%5(%4)", op); } } - else - { - /* Setup base pointer if required. */ - if (!vcall_offset - || (!DISP_IN_RANGE (delta) - && !CONST_OK_FOR_K (delta) - && !CONST_OK_FOR_Os (delta)) - || (!DISP_IN_RANGE (delta) - && !CONST_OK_FOR_K (vcall_offset) - && !CONST_OK_FOR_Os (vcall_offset))) - { - op[5] = gen_label_rtx (); - output_asm_insn ("basr\t%4,0", op); - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[5])); - } - - /* Add DELTA to this pointer. */ - if (delta) - { - if (CONST_OK_FOR_J (delta)) - output_asm_insn ("la\t%1,%2(%1)", op); - else if (DISP_IN_RANGE (delta)) - output_asm_insn ("lay\t%1,%2(%1)", op); - else if (CONST_OK_FOR_K (delta)) - output_asm_insn ("ahi\t%1,%2", op); - else if (CONST_OK_FOR_Os (delta)) - output_asm_insn ("afi\t%1,%2", op); - else - { - op[6] = gen_label_rtx (); - output_asm_insn ("a\t%1,%6-%5(%4)", op); - } - } - /* Perform vcall adjustment. */ - if (vcall_offset) + /* Perform vcall adjustment. */ + if (vcall_offset) + { + if (DISP_IN_RANGE (vcall_offset)) { - if (CONST_OK_FOR_J (vcall_offset)) - { - output_asm_insn ("l\t%4,0(%1)", op); - output_asm_insn ("a\t%1,%3(%4)", op); - } - else if (DISP_IN_RANGE (vcall_offset)) - { - output_asm_insn ("l\t%4,0(%1)", op); - output_asm_insn ("ay\t%1,%3(%4)", op); - } - else if (CONST_OK_FOR_K (vcall_offset)) - { - output_asm_insn ("lhi\t%4,%3", op); - output_asm_insn ("a\t%4,0(%1)", op); - output_asm_insn ("a\t%1,0(%4)", op); - } - else if (CONST_OK_FOR_Os (vcall_offset)) - { - output_asm_insn ("iilf\t%4,%3", op); - output_asm_insn ("a\t%4,0(%1)", op); - output_asm_insn ("a\t%1,0(%4)", op); - } - else - { - op[7] = gen_label_rtx (); - output_asm_insn ("l\t%4,%7-%5(%4)", op); - output_asm_insn ("a\t%4,0(%1)", op); - output_asm_insn ("a\t%1,0(%4)", op); - } - - /* We had to clobber the base pointer register. - Re-setup the base pointer (with a different base). */ - op[5] = gen_label_rtx (); - output_asm_insn ("basr\t%4,0", op); - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[5])); + output_asm_insn ("lg\t%4,0(%1)", op); + output_asm_insn ("ag\t%1,%3(%4)", op); } - - /* Jump to target. */ - op[8] = gen_label_rtx (); - - if (!flag_pic) - output_asm_insn ("l\t%4,%8-%5(%4)", op); - else if (!nonlocal) - output_asm_insn ("a\t%4,%8-%5(%4)", op); - /* We cannot call through .plt, since .plt requires %r12 loaded. */ - else if (flag_pic == 1) + else if (CONST_OK_FOR_K (vcall_offset)) { - output_asm_insn ("a\t%4,%8-%5(%4)", op); - output_asm_insn ("l\t%4,%0(%4)", op); + output_asm_insn ("lghi\t%4,%3", op); + output_asm_insn ("ag\t%4,0(%1)", op); + output_asm_insn ("ag\t%1,0(%4)", op); } - else if (flag_pic == 2) + else if (CONST_OK_FOR_Os (vcall_offset)) { - op[9] = gen_rtx_REG (Pmode, 0); - output_asm_insn ("l\t%9,%8-4-%5(%4)", op); - output_asm_insn ("a\t%4,%8-%5(%4)", op); - output_asm_insn ("ar\t%4,%9", op); - output_asm_insn ("l\t%4,0(%4)", op); + output_asm_insn ("lgfi\t%4,%3", op); + output_asm_insn ("ag\t%4,0(%1)", op); + output_asm_insn ("ag\t%1,0(%4)", op); } - - output_asm_insn ("br\t%4", op); - - /* Output literal pool. */ - output_asm_insn (".align\t4", op); - - if (nonlocal && flag_pic == 2) - output_asm_insn (".long\t%0", op); - if (nonlocal) + else { - op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); - SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL; + op[7] = gen_label_rtx (); + output_asm_insn ("llgf\t%4,%7-%5(%4)", op); + output_asm_insn ("ag\t%4,0(%1)", op); + output_asm_insn ("ag\t%1,0(%4)", op); } + } - targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8])); - if (!flag_pic) - output_asm_insn (".long\t%0", op); - else - output_asm_insn (".long\t%0-%5", op); + /* Jump to target. */ + output_asm_insn ("jg\t%0%K0", op); - if (op[6]) - { - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[6])); - output_asm_insn (".long\t%2", op); - } - if (op[7]) - { - targetm.asm_out.internal_label (file, "L", - CODE_LABEL_NUMBER (op[7])); - output_asm_insn (".long\t%3", op); - } + /* Output literal pool if required. */ + if (op[5]) + { + output_asm_insn (".align\t4", op); + targetm.asm_out.internal_label (file, "L", + CODE_LABEL_NUMBER (op[5])); + } + if (op[6]) + { + targetm.asm_out.internal_label (file, "L", + CODE_LABEL_NUMBER (op[6])); + output_asm_insn (".long\t%2", op); } + if (op[7]) + { + targetm.asm_out.internal_label (file, "L", + CODE_LABEL_NUMBER (op[7])); + output_asm_insn (".long\t%3", op); + } + final_end_function (); assemble_end_function (thunk, fnname); } @@ -14739,24 +14333,18 @@ s390_indirect_branch_via_inline_thunk (rtx execute_target) ASM_OUTPUT_LABEL (asm_out_file, label); } - if (!TARGET_ZARCH) - fputs ("\t.machinemode zarch\n", asm_out_file); - if (REG_P (execute_target)) fprintf (asm_out_file, "\tex\t%%r0,0(%%r%d)\n", REGNO (execute_target)); else output_asm_insn ("\texrl\t%%r0,%0", &execute_target); - if (!TARGET_ZARCH) - fputs ("\t.machinemode esa\n", asm_out_file); - fputs ("0:\tj\t0b\n", asm_out_file); } static bool s390_valid_pointer_mode (scalar_int_mode mode) { - return (mode == SImode || (TARGET_64BIT && mode == DImode)); + return mode == SImode || mode == DImode; } /* Checks whether the given CALL_EXPR would use a caller @@ -14802,7 +14390,7 @@ s390_call_saved_register_used (tree call_expr) if (REG_P (parm_rtx)) { int size = s390_function_arg_size (arg.mode, arg.type); - int nregs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; + int nregs = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; for (reg = 0; reg < nregs; reg++) if (!call_used_or_fixed_reg_p (reg + REGNO (parm_rtx))) @@ -14863,11 +14451,6 @@ s390_function_ok_for_sibcall (tree decl, tree exp) if (TARGET_TPF_PROFILING) return false; - /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved) - which would have to be restored before the sibcall. */ - if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl)) - return false; - /* The thunks for indirect branches require r1 if no exrl is available. r1 might not be available when doing a sibling call. */ @@ -14908,7 +14491,6 @@ rtx_insn * s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, rtx retaddr_reg) { - bool plt31_call_p = false; rtx_insn *insn; rtx vec[4] = { NULL_RTX }; int elts = 0; @@ -14918,49 +14500,18 @@ s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, rtx *clobber_thunk_reg = &vec[3]; int i; - /* Direct function calls need special treatment. */ - if (GET_CODE (addr_location) == SYMBOL_REF) - { - /* When calling a global routine in PIC mode, we must - replace the symbol itself with the PLT stub. */ - if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location) && !TARGET_64BIT) - { - if (retaddr_reg != NULL_RTX) - { - addr_location = gen_rtx_UNSPEC (Pmode, - gen_rtvec (1, addr_location), - UNSPEC_PLT31); - addr_location = gen_rtx_CONST (Pmode, addr_location); - plt31_call_p = true; - } - else - /* For -fpic code the PLT entries might use r12 which is - call-saved. Therefore we cannot do a sibcall when - calling directly using a symbol ref. When reaching - this point we decided (in s390_function_ok_for_sibcall) - to do a sibcall for a function pointer but one of the - optimizers was able to get rid of the function pointer - by propagating the symbol ref into the call. This - optimization is illegal for S/390 so we turn the direct - call into a indirect call again. */ - addr_location = force_reg (Pmode, addr_location); - } - } - /* If it is already an indirect call or the code above moved the SYMBOL_REF to somewhere else make sure the address can be found in register 1. */ if (retaddr_reg == NULL_RTX - && GET_CODE (addr_location) != SYMBOL_REF - && !plt31_call_p) + && GET_CODE (addr_location) != SYMBOL_REF) { emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location); addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM); } if (TARGET_INDIRECT_BRANCH_NOBP_CALL - && GET_CODE (addr_location) != SYMBOL_REF - && !plt31_call_p) + && GET_CODE (addr_location) != SYMBOL_REF) { /* Indirect branch thunks require the target to be a single GPR. */ addr_location = force_reg (Pmode, addr_location); @@ -15011,8 +14562,8 @@ s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, insn = emit_call_insn (*call); - /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */ - if (plt31_call_p || tls_call != NULL_RTX) + /* tls calls use the GOT register implicitly. */ + if (tls_call != NULL_RTX) { /* s390_function_ok_for_sibcall should have denied sibcalls in this case. */ @@ -15033,16 +14584,9 @@ s390_conditional_register_usage (void) fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; fixed_regs[BASE_REGNUM] = 0; fixed_regs[RETURN_REGNUM] = 0; - if (TARGET_64BIT) - { - for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) - call_used_regs[i] = 0; - } - else - { - call_used_regs[FPR4_REGNUM] = 0; - call_used_regs[FPR6_REGNUM] = 0; - } + + for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) + call_used_regs[i] = 0; if (TARGET_SOFT_FLOAT) { @@ -15188,7 +14732,7 @@ s390_optimize_prologue (void) if (cfun_frame_layout.first_save_gpr != -1) save_gprs (base, off + (cfun_frame_layout.first_save_gpr - - first) * UNITS_PER_LONG, + - first) * UNITS_PER_WORD, cfun_frame_layout.first_save_gpr, cfun_frame_layout.last_save_gpr, insn); @@ -15244,7 +14788,7 @@ s390_optimize_prologue (void) { rtx rpat = restore_gprs (base, off + (cfun_frame_layout.first_restore_gpr - - first) * UNITS_PER_LONG, + - first) * UNITS_PER_WORD, cfun_frame_layout.first_restore_gpr, cfun_frame_layout.last_restore_gpr); @@ -16602,15 +16146,6 @@ static void s390_option_override_internal (struct gcc_options *opts, struct gcc_options *opts_set) { - /* Architecture mode defaults according to ABI. */ - if (!(opts_set->x_target_flags & MASK_ZARCH)) - { - if (TARGET_64BIT) - opts->x_target_flags |= MASK_ZARCH; - else - opts->x_target_flags &= ~MASK_ZARCH; - } - /* Set the march default in case it hasn't been specified on cmdline. */ if (!opts_set->x_s390_arch) opts->x_s390_arch = PROCESSOR_2064_Z900; @@ -16627,8 +16162,6 @@ s390_option_override_internal (struct gcc_options *opts, if (opts->x_s390_arch == PROCESSOR_NATIVE || opts->x_s390_tune == PROCESSOR_NATIVE) gcc_unreachable (); - if (TARGET_64BIT && !TARGET_ZARCH_P (opts->x_target_flags)) - error ("64-bit ABI not supported in ESA/390 mode"); if (opts->x_s390_indirect_branch == indirect_branch_thunk_inline || opts->x_s390_indirect_branch_call == indirect_branch_thunk_inline @@ -16656,10 +16189,10 @@ s390_option_override_internal (struct gcc_options *opts, } /* Enable hardware transactions if available and not explicitly - disabled by user. E.g. with -m31 -march=zEC12 -mzarch */ + disabled by user. E.g. with -march=zEC12. */ if (!TARGET_OPT_HTM_P (opts_set->x_target_flags)) { - if (TARGET_CPU_HTM_P (opts) && TARGET_ZARCH_P (opts->x_target_flags)) + if (TARGET_CPU_HTM_P (opts)) opts->x_target_flags |= MASK_OPT_HTM; else opts->x_target_flags &= ~MASK_OPT_HTM; @@ -16679,16 +16212,15 @@ s390_option_override_internal (struct gcc_options *opts, } else { - if (TARGET_CPU_VX_P (opts) && TARGET_ZARCH_P (opts->x_target_flags)) + if (TARGET_CPU_VX_P (opts)) /* Enable vector support if available and not explicitly disabled - by user. E.g. with -m31 -march=z13 -mzarch */ + by user. E.g. with -march=z13. */ opts->x_target_flags |= MASK_OPT_VX; else opts->x_target_flags &= ~MASK_OPT_VX; } - /* Use hardware DFP if available and not explicitly disabled by - user. E.g. with -m31 -march=z10 -mzarch */ + /* Use hardware DFP if available and not explicitly disabled by user. */ if (!TARGET_HARD_DFP_P (opts_set->x_target_flags)) { if (TARGET_DFP_P (opts)) @@ -16705,9 +16237,6 @@ s390_option_override_internal (struct gcc_options *opts, error ("hardware decimal floating-point instructions" " not available on %s", processor_table[(int)opts->x_s390_arch].name); - if (!TARGET_ZARCH_P (opts->x_target_flags)) - error ("hardware decimal floating-point instructions" - " not available in ESA/390 mode"); } else opts->x_target_flags &= ~MASK_HARD_DFP; @@ -16807,6 +16336,11 @@ s390_option_override_internal (struct gcc_options *opts, else SET_OPTION_IF_UNSET (opts, opts_set, param_vect_partial_vector_usage, 0); + if (flag_m31) + error ("%<-m31%> is no longer supported"); + if (flag_mesa) + error ("%<-mesa%> is no longer supported"); + /* Set the default alignment. */ s390_default_align (opts); @@ -16816,12 +16350,6 @@ s390_option_override_internal (struct gcc_options *opts, /* Call target specific restore function to do post-init work. At the moment, this just sets opts->x_s390_cost_pointer. */ s390_function_specific_restore (opts, opts_set, NULL); - - /* Check whether -mfentry is supported. It cannot be used in 31-bit mode, - because 31-bit PLT stubs assume that %r12 contains GOT address, which is - not the case when the code runs before the prolog. */ - if (opts->x_flag_fentry && !TARGET_64BIT) - error ("%<-mfentry%> is supported only for 64-bit CPUs"); } static void @@ -17251,8 +16779,7 @@ s390_can_inline_p (tree caller, tree callee) /* Flags which affect the ABI and in general prevent inlining. */ unsigned HOST_WIDE_INT must_match_masks - = (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_SOFT_FLOAT - | MASK_LONG_DOUBLE_128 | MASK_OPT_VX); + = (MASK_HARD_DFP | MASK_SOFT_FLOAT | MASK_LONG_DOUBLE_128 | MASK_OPT_VX); /* Flags which we in general want to prevent inlining but accept for always_inline. */ @@ -17459,8 +16986,7 @@ s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, enum by_pieces_operation op ATTRIBUTE_UNUSED, bool speed_p ATTRIBUTE_UNUSED) { - return (size == 1 || size == 2 - || size == 4 || (TARGET_ZARCH && size == 8)); + return size == 1 || size == 2 || size == 4 || size == 8; } /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */ @@ -17566,7 +17092,7 @@ s390_preferred_simd_mode (scalar_mode mode) return V16QImode; default:; } - return word_mode; + return DImode; } /* Our hardware does not require vectors to be strictly aligned. */ @@ -17829,16 +17355,8 @@ s390_rawmemchr (machine_mode elt_mode, rtx dst, rtx src, rtx pat) emit_label (loop_end); LABEL_NUSES (loop_end) = 1; - if (TARGET_64BIT) - { - lens = convert_to_mode (V2DImode, lens, 1); - emit_insn (gen_vec_extractv2didi (offset, lens, GEN_INT (0))); - } - else - { - lens = convert_to_mode (V4SImode, lens, 1); - emit_insn (gen_vec_extractv4sisi (offset, lens, GEN_INT (1))); - } + lens = convert_to_mode (V2DImode, lens, 1); + emit_insn (gen_vec_extractv2didi (offset, lens, GEN_INT (0))); force_expand_binop (Pmode, add_optab, addr, offset, dst, 1, OPTAB_DIRECT); } @@ -17847,7 +17365,7 @@ s390_rawmemchr (machine_mode elt_mode, rtx dst, rtx src, rtx pat) static unsigned HOST_WIDE_INT s390_asan_shadow_offset (void) { - return TARGET_64BIT ? HOST_WIDE_INT_1U << 52 : HOST_WIDE_INT_UC (0x20000000); + return HOST_WIDE_INT_1U << 52; } #ifdef HAVE_GAS_HIDDEN @@ -17932,17 +17450,9 @@ s390_output_indirect_thunk_function (unsigned int regno, bool z10_p) fputs ("\t.machine push\n", asm_out_file); fputs ("\t.machine z10\n", asm_out_file); } - /* We use exrl even if -mzarch hasn't been specified on the - command line so we have to tell the assembler to accept - it. */ - if (!TARGET_ZARCH) - fputs ("\t.machinemode zarch\n", asm_out_file); fputs ("\texrl\t0,1f\n", asm_out_file); - if (!TARGET_ZARCH) - fputs ("\t.machinemode esa\n", asm_out_file); - if (!TARGET_CPU_Z10) fputs ("\t.machine pop\n", asm_out_file); } @@ -18853,8 +18363,6 @@ s390_c_mode_for_floating_type (enum tree_index ti) bool s390_bitint_type_info (int n, struct bitint_info *info) { - if (!TARGET_64BIT) - return false; if (n <= 8) info->limb_mode = QImode; else if (n <= 16) diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 4764a87c7a6b..2ca7689b0962 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -53,8 +53,7 @@ enum processor_flags #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_9175_Z17 ? PROCESSOR_9175_Z17 : s390_tune )) /* These flags indicate that the generated code should run on a cpu - providing the respective hardware facility regardless of the - current cpu mode (ESA or z/Architecture). */ + providing the respective hardware facility. */ #define TARGET_CPU_IEEE_FLOAT \ (s390_arch_flags & PF_IEEE_FLOAT) @@ -135,72 +134,46 @@ enum processor_flags providing the respective hardware facility when run in z/Architecture mode. */ -#define TARGET_LONG_DISPLACEMENT \ - (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) +#define TARGET_LONG_DISPLACEMENT TARGET_CPU_LONG_DISPLACEMENT #define TARGET_LONG_DISPLACEMENT_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) \ - && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) -#define TARGET_EXTIMM \ - (TARGET_ZARCH && TARGET_CPU_EXTIMM) -#define TARGET_EXTIMM_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) -#define TARGET_DFP \ - (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) + (TARGET_CPU_LONG_DISPLACEMENT_P (opts)) +#define TARGET_EXTIMM TARGET_CPU_EXTIMM +#define TARGET_EXTIMM_P(opts) (TARGET_CPU_EXTIMM_P (opts)) +#define TARGET_DFP (TARGET_CPU_DFP && TARGET_HARD_FLOAT) #define TARGET_DFP_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ + (TARGET_CPU_DFP_P (opts) \ && TARGET_HARD_FLOAT_P (opts->x_target_flags)) -#define TARGET_Z10 \ - (TARGET_ZARCH && TARGET_CPU_Z10) -#define TARGET_Z10_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) -#define TARGET_Z196 \ - (TARGET_ZARCH && TARGET_CPU_Z196) -#define TARGET_Z196_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) -#define TARGET_ZEC12 \ - (TARGET_ZARCH && TARGET_CPU_ZEC12) -#define TARGET_ZEC12_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) +#define TARGET_Z10 TARGET_CPU_Z10 +#define TARGET_Z10_P(opts) (TARGET_CPU_Z10_P (opts)) +#define TARGET_Z196 TARGET_CPU_Z196 +#define TARGET_Z196_P(opts) (TARGET_CPU_Z196_P (opts)) +#define TARGET_ZEC12 TARGET_CPU_ZEC12 +#define TARGET_ZEC12_P(opts) (TARGET_CPU_ZEC12_P (opts)) #define TARGET_HTM (TARGET_OPT_HTM) #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) -#define TARGET_Z13 \ - (TARGET_ZARCH && TARGET_CPU_Z13) -#define TARGET_Z13_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) -#define TARGET_VX \ - (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) +#define TARGET_Z13 TARGET_CPU_Z13 +#define TARGET_Z13_P(opts) (TARGET_CPU_Z13_P (opts)) +#define TARGET_VX (TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) #define TARGET_VX_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ + (TARGET_CPU_VX_P (opts) \ && TARGET_OPT_VX_P (opts->x_target_flags) \ && TARGET_HARD_FLOAT_P (opts->x_target_flags)) -#define TARGET_Z14 (TARGET_ZARCH && TARGET_CPU_Z14) -#define TARGET_Z14_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z14_P (opts)) -#define TARGET_VXE \ - (TARGET_VX && TARGET_CPU_VXE) -#define TARGET_VXE_P(opts) \ - (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) -#define TARGET_Z15 (TARGET_ZARCH && TARGET_CPU_Z15) -#define TARGET_Z15_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z15_P (opts)) -#define TARGET_VXE2 \ - (TARGET_VX && TARGET_CPU_VXE2) -#define TARGET_VXE2_P(opts) \ - (TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts)) -#define TARGET_Z16 (TARGET_ZARCH && TARGET_CPU_Z16) -#define TARGET_Z16_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z16_P (opts)) -#define TARGET_NNPA \ - (TARGET_ZARCH && TARGET_CPU_NNPA) -#define TARGET_NNPA_P(opts) \ - (TARGET_ZARCH_P (opts) && TARGET_CPU_NNPA_P (opts)) -#define TARGET_VXE3 \ - (TARGET_VX && TARGET_CPU_VXE3) -#define TARGET_VXE3_P(opts) \ - (TARGET_VX_P (opts) && TARGET_CPU_VXE3_P (opts)) -#define TARGET_Z17 (TARGET_ZARCH && TARGET_CPU_Z17) -#define TARGET_Z17_P(opts) \ - (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z17_P (opts)) +#define TARGET_Z14 TARGET_CPU_Z14 +#define TARGET_Z14_P(opts) (TARGET_CPU_Z14_P (opts)) +#define TARGET_VXE (TARGET_VX && TARGET_CPU_VXE) +#define TARGET_VXE_P(opts) (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) +#define TARGET_Z15 TARGET_CPU_Z15 +#define TARGET_Z15_P(opts) (TARGET_CPU_Z15_P (opts)) +#define TARGET_VXE2 (TARGET_VX && TARGET_CPU_VXE2) +#define TARGET_VXE2_P(opts) (TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts)) +#define TARGET_Z16 TARGET_CPU_Z16 +#define TARGET_Z16_P(opts) (TARGET_CPU_Z16_P (opts)) +#define TARGET_NNPA TARGET_CPU_NNPA +#define TARGET_NNPA_P(opts) (TARGET_CPU_NNPA_P (opts)) +#define TARGET_VXE3 (TARGET_VX && TARGET_CPU_VXE3) +#define TARGET_VXE3_P(opts) (TARGET_VX_P (opts) && TARGET_CPU_VXE3_P (opts)) +#define TARGET_Z17 TARGET_CPU_Z17 +#define TARGET_Z17_P(opts) (TARGET_CPU_Z17_P (opts)) #if defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13) #define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z13 @@ -267,18 +240,12 @@ enum processor_flags /* Target CPU builtins. */ #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) -#ifdef DEFAULT_TARGET_64BIT -#define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ - | MASK_OPT_HTM | MASK_OPT_VX) -#else -#define TARGET_DEFAULT 0 -#endif +#define TARGET_DEFAULT (MASK_HARD_DFP | MASK_OPT_HTM | MASK_OPT_VX) /* Support for configure-time defaults. The order here is important so that -march doesn't squash the tune values. */ #define OPTION_DEFAULT_SPECS \ - { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ { "tune", "%{!mtune=*:%{!march=*:-mtune=%(VALUE)}}" }, \ { "arch", "%{!march=*:-march=%(VALUE)}" } @@ -290,22 +257,14 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); #define MARCH_MTUNE_NATIVE_SPECS \ "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ "%{march=native:%<march=native" \ - " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" + " %:local_cpu_detect(arch)}" #else # define MARCH_MTUNE_NATIVE_SPECS "" #endif -#ifdef DEFAULT_TARGET_64BIT -#define S390_TARGET_BITS_STRING "64" -#else -#define S390_TARGET_BITS_STRING "31" -#endif - /* Defaulting rules. */ #define DRIVER_SELF_SPECS \ MARCH_MTUNE_NATIVE_SPECS, \ - "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ - "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ "%{!march=*:-march=z900}" /* Target machine storage layout. */ @@ -322,34 +281,14 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); being accessed. */ #define STACK_CHECK_MOVING_SP 1 -#ifndef IN_LIBGCC2 - /* Width of a word, in units (bytes). */ - #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) - -/* Width of a pointer. To be used instead of UNITS_PER_WORD in - ABI-relevant contexts. This always matches - GET_MODE_SIZE (Pmode). */ - #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) - #define MIN_UNITS_PER_WORD 4 - #define MAX_BITS_PER_WORD 64 -#else - - /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether - the library should export TImode functions or not. Thus, we have - to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ - #ifdef __s390x__ - #define UNITS_PER_WORD 8 - #else - #define UNITS_PER_WORD 4 - #endif -#endif +#define UNITS_PER_WORD 8 /* Width of a pointer, in bits. */ -#define POINTER_SIZE (TARGET_64BIT ? 64 : 32) +#define POINTER_SIZE 64 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) +#define PARM_BOUNDARY 64 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 64 @@ -375,7 +314,7 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); NONLOCAL needs twice Pmode to maintain both backchain and SP. */ #define STACK_SAVEAREA_MODE(LEVEL) \ ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ - : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) + : (LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) /* Type layout. */ @@ -383,7 +322,7 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); /* Sizes in bits of the source language data types. */ #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 -#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) +#define LONG_TYPE_SIZE 64 #define LONG_LONG_TYPE_SIZE 64 /* We use "unsigned char" as default. */ @@ -448,8 +387,7 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); The 'fake' hard registers are call-clobbered and fixed. The access registers are call-saved and fixed. - On 31-bit, FPRs 18-19 are call-clobbered; - on 64-bit, FPRs 24-31 are call-clobbered. + FPRs 24-31 are call-clobbered. The remaining FPRs are call-saved. All non-FP vector registers are call-clobbered v16-v31. */ @@ -615,7 +553,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; dynamic allocations (alloca), and finally the local variables. */ /* Offset from stack-pointer to first location of outgoing args. */ -#define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) +#define STACK_POINTER_OFFSET 160 /* Offset from the stack pointer register to an item dynamically allocated on the stack, e.g., by `alloca'. */ @@ -639,7 +577,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ (TARGET_PACKED_STACK ? \ plus_constant (Pmode, (FRAME), \ - STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) + STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME)) /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of builtin_frame_address. Otherwise arg pointer - @@ -654,9 +592,6 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; #define RETURN_ADDR_RTX(COUNT, FRAME) \ s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) -/* In 31-bit mode, we need to mask off the high bit of return addresses. */ -#define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) - /* Exception handling. */ @@ -676,7 +611,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; : DW_EH_PE_absptr) /* Register save slot alignment. */ -#define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) +#define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_WORD) /* Let the assembler generate debug line info. */ #define DWARF2_ASM_LINE_DEBUG_INFO 1 @@ -744,11 +679,10 @@ CUMULATIVE_ARGS; #define LAST_VEC_ARG_REGNO 53 /* Arguments can be placed in general registers 2 to 6, or in floating - point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 - bit. */ + point registers 0, 2, 4 and 6. */ #define FUNCTION_ARG_REGNO_P(N) \ (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ - || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ + || ((N) == 18 || (N) == 19) \ || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) @@ -776,7 +710,7 @@ CUMULATIVE_ARGS; /* Trampolines for nested functions. */ -#define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) +#define TRAMPOLINE_SIZE 32 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD /* Addressing modes, and classification of registers for them. */ @@ -836,12 +770,12 @@ CUMULATIVE_ARGS; /* An integer expression for the size in bits of the largest integer machine mode that should actually be used. We allow pairs of registers. */ -#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) /* The maximum number of bytes that a single instruction can move quickly between memory and registers or between two memory locations. */ -#define MOVE_MAX (TARGET_ZARCH ? 16 : 8) -#define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) +#define MOVE_MAX 16 +#define MOVE_MAX_PIECES 8 #define MAX_MOVE_MAX 16 /* Don't perform CSE on function addresses. */ @@ -851,11 +785,8 @@ CUMULATIVE_ARGS; to split a struct move into several word-size moves. For S/390 only small values make sense here since struct moves are relatively cheap thanks to mvc so the small default value chosen for archs - with memmove patterns should be ok. But this value is multiplied - in tree-sra with UNITS_PER_WORD to make a decision so we adjust it - here to compensate for that factor since mvc costs exactly the same - on 31 and 64 bit. */ -#define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) + with memmove patterns should be ok. */ +#define MOVE_RATIO(speed) 2 /* Sections. */ @@ -869,18 +800,6 @@ CUMULATIVE_ARGS; /* Output before writable (uninitialized) data. */ #define BSS_SECTION_ASM_OP ".bss" -/* S/390 constant pool breaks the devices in crtstuff.c to control section - in where code resides. We have to write it as asm code. */ -#ifndef __s390x__ -#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ - asm (SECTION_OP "\n\ - bras\t%r2,1f\n\ -0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ -1: l\t%r3,0(%r2)\n\ - bas\t%r14,0(%r3,%r2)\n\ - .previous"); -#endif - /* Position independent code. */ @@ -945,7 +864,7 @@ CUMULATIVE_ARGS; #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ do { \ char buf[32]; \ - fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ + fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ assemble_name ((FILE), buf); \ fputc ('\n', (FILE)); \ @@ -955,7 +874,7 @@ do { \ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ do { \ char buf[32]; \ - fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ + fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ assemble_name ((FILE), buf); \ fputc ('-', (FILE)); \ @@ -986,15 +905,12 @@ do { \ /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) +#define CASE_VECTOR_MODE DImode /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ -#define Pmode (TARGET_64BIT ? DImode : SImode) - -/* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ -#define POINTERS_EXTEND_UNSIGNED -1 +#define Pmode DImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 3b6ea26cbc22..587077b84fa6 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -79,7 +79,6 @@ UNSPEC_GOTENT UNSPEC_GOT UNSPEC_GOTOFF - UNSPEC_PLT31 UNSPEC_PLTOFF ; Literal pool @@ -610,7 +609,7 @@ (const (symbol_ref "s390_tune_attr"))) (define_attr "cpu_facility" - "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2,z16,nnpa,vxe3,z17" + "standard,ieee,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2,z16,nnpa,vxe3,z17" (const_string "standard")) (define_attr "enabled" "" @@ -621,10 +620,6 @@ (match_test "TARGET_CPU_IEEE_FLOAT")) (const_int 1) - (and (eq_attr "cpu_facility" "zarch") - (match_test "TARGET_ZARCH")) - (const_int 1) - (and (eq_attr "cpu_facility" "longdisp") (match_test "TARGET_LONG_DISPLACEMENT")) (const_int 1) @@ -637,9 +632,6 @@ (match_test "TARGET_DFP")) (const_int 1) - (eq_attr "cpu_facility" "cpu_zarch") - (const_int 1) - (and (eq_attr "cpu_facility" "z10") (match_test "TARGET_Z10")) (const_int 1) @@ -774,34 +766,20 @@ ; 32 bit int<->fp conversion instructions are available since VXE2 (z15). (define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")]) -;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated +;; These mode iterators allow 32-bit and 64-bit GPR patterns to be generated ;; from the same template. -(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) -(define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) +(define_mode_iterator TDSI [TI DI SI]) (define_mode_iterator DSI [DI SI]) (define_mode_iterator TDI [TI DI]) -;; These mode iterators allow :P to be used for patterns that operate on -;; pointer-sized quantities. Exactly one of the two alternatives will match. -(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) - -;; These macros refer to the actual word_mode of the configuration. -;; This is equal to Pmode except on 31-bit machines in zarch mode. -(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) -(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) - -;; Used by the umul pattern to express modes having half the size. -(define_mode_attr DWH [(TI "DI") (DI "SI")]) -(define_mode_attr dwh [(TI "di") (DI "si")]) - ;; This mode iterator allows the QI and HI patterns to be defined from ;; the same template. (define_mode_iterator HQI [HI QI]) ;; This mode iterator allows the integer patterns to be defined from the ;; same template. -(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) -(define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) +(define_mode_iterator INT [DI SI HI QI]) +(define_mode_iterator DINT [TI DI SI HI QI]) (define_mode_iterator SINT [SI HI QI]) ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from @@ -893,12 +871,12 @@ (define_mode_attr _d [(TF "") (FPRX2 "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) -;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode -;; and "0" in SImode. This allows to combine instructions of which the 31bit +;; In DSI templates, a constraint like "<d0>" will expand to "d" in DImode +;; and "0" in SImode. This allows to combine instructions of which the 32bit ;; version only operates on one register. (define_mode_attr d0 [(DI "d") (SI "0")]) -;; In combination with d0 this allows to combine instructions of which the 31bit +;; In combination with d0 this allows to combine instructions of which the 32bit ;; version only operates on one register. The DImode version needs an additional ;; register for the assembler output. (define_mode_attr 1 [(DI "%1,") (SI "")]) @@ -923,28 +901,24 @@ ;; in "RSE" for TImode and "RS" for DImode. (define_mode_attr TE [(TI "E") (DI "")]) -;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode +;; In DSI templates, a string like "lc<g>r" will expand to "lcgr" in DImode ;; and "lcr" in SImode. (define_mode_attr g [(DI "g") (SI "")]) -;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode +;; In DSI templates, a string like "sl<y>" will expand to "slg" in DImode ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions -;; were enhanced with long displacements whereas 31bit instructions got a ..y +;; were enhanced with long displacements whereas 32bit instructions got a ..y ;; variant for long displacements. (define_mode_attr y [(DI "g") (SI "y")]) -;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode -;; and "cds" in DImode. -(define_mode_attr tg [(TI "g") (DI "")]) - ;; In TDI templates, a string like "c<d>sg". (define_mode_attr td [(TI "d") (DI "")]) -;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode +;; In DSI templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode ;; and "cfdbr" in SImode. (define_mode_attr gf [(DI "g") (SI "f") (DF "g") (SF "f")]) -;; In GPR templates, a string like sll<gk> will expand to sllg for DI +;; In DSI templates, a string like sll<gk> will expand to sllg for DI ;; and sllk for SI. This way it is possible to merge the new z196 SI ;; 3 operands shift instructions into the existing patterns. (define_mode_attr gk [(DI "g") (SI "k")]) @@ -1039,8 +1013,7 @@ (match_operand:DI 1 "immediate_operand" "N0HD0,N1HD0,N2HD0,N3HD0")) (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] - "TARGET_ZARCH - && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) + "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) && s390_single_part (operands[1], DImode, HImode, 0) >= 0" "@ tmhh\t%0,%i1 @@ -1089,7 +1062,7 @@ (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d,d") (sign_extend:DI (match_dup 0)))] - "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCSmode)" "ltgfr\t%2,%0 ltgf\t%2,%0" [(set_attr "op_type" "RRE,RXY") @@ -1099,9 +1072,9 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") - (match_operand:GPR 1 "const0_operand" ""))) - (set (match_operand:GPR 2 "register_operand" "=d,d") + (compare (match_operand:DSI 0 "nonimmediate_operand" "d,T") + (match_operand:DSI 1 "const0_operand" ""))) + (set (match_operand:DSI 2 "register_operand" "=d,d") (match_dup 0))] "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" "@ @@ -1113,10 +1086,10 @@ ; Peephole to combine a load-and-test from volatile memory which combine does ; not do. (define_peephole2 - [(set (match_operand:GPR 0 "register_operand") - (match_operand:GPR 2 "memory_operand")) + [(set (match_operand:DSI 0 "register_operand") + (match_operand:DSI 2 "memory_operand")) (set (reg CC_REGNUM) - (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] + (compare (match_dup 0) (match_operand:DSI 1 "const0_operand")))] "s390_match_ccmode (peep2_next_insn (1), CCSmode) && TARGET_EXTIMM && GENERAL_REG_P (operands[0]) && satisfies_constraint_T (operands[2]) @@ -1129,9 +1102,9 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_cconly_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") - (match_operand:GPR 1 "const0_operand" ""))) - (clobber (match_scratch:GPR 2 "=X,d"))] + (compare (match_operand:DSI 0 "nonimmediate_operand" "d,T") + (match_operand:DSI 1 "const0_operand" ""))) + (clobber (match_scratch:DSI 2 "=X,d"))] "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" "@ lt<g>r\t%0,%0 @@ -1145,7 +1118,7 @@ (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d") (match_dup 0))] - "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" + "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" "ltgr\t%2,%0" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_fr_E1")]) @@ -1179,20 +1152,11 @@ (set_attr "cpu_facility" "*,*,longdisp") (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) -(define_insn "*tstdi_cconly_31" - [(set (reg CC_REGNUM) - (compare (match_operand:DI 0 "register_operand" "d") - (match_operand:DI 1 "const0_operand" "")))] - "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" - "srda\t%0,0" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - ; ltr, ltgr (define_insn "*tst<mode>_cconly2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "register_operand" "d") - (match_operand:GPR 1 "const0_operand" "")))] + (compare (match_operand:DSI 0 "register_operand" "d") + (match_operand:DSI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "lt<g>r\t%0,%0" [(set_attr "op_type" "RR<E>") @@ -1276,7 +1240,7 @@ [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] - "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCTmode)" "@ cgr\t%0,%1 cghi\t%0,%h1 @@ -1309,7 +1273,7 @@ (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")) (match_operand:DI 0 "register_operand" "d, d,d")))] - "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCSRmode)" "@ cgfr\t%0,%1 cgf\t%0,%1 @@ -1348,7 +1312,7 @@ (define_insn "*cmpdi_ccs_signhi_rl" [(set (reg CC_REGNUM) (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) - (match_operand:GPR 0 "register_operand" "d,d")))] + (match_operand:DSI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" "@ cgh\t%0,%1 @@ -1360,9 +1324,9 @@ ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl (define_insn "*cmp<mode>_ccs" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" + (compare (match_operand:DSI 0 "nonimmediate_operand" "d,d,Q, d,d,d,d") - (match_operand:GPR 1 "general_operand" + (match_operand:DSI 1 "general_operand" "d,K,K,Os,R,T,b")))] "s390_match_ccmode(insn, CCSmode)" "@ @@ -1395,11 +1359,11 @@ (set_attr "relative_long" "yes")]) ; clhrl, clghrl -(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" +(define_insn "*cmp<DSI:mode>_ccu_zerohi_rldi" [(set (reg CC_REGNUM) - (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 + (compare (zero_extend:DSI (mem:HI (match_operand:DI 1 "larl_operand" "X"))) - (match_operand:GPR 0 "register_operand" "d")))] + (match_operand:DSI 0 "register_operand" "d")))] "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "cl<g>hrl\t%0,%1" [(set_attr "op_type" "RIL") @@ -1412,7 +1376,7 @@ (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")) (match_operand:DI 0 "register_operand" "d,d,d")))] - "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCURmode)" "@ clgfr\t%0,%1 clgf\t%0,%1 @@ -1429,7 +1393,7 @@ "d, d,d,Q,d, Q,BQ") (match_operand:DI 1 "general_operand" "d,Op,b,D,T,BQ,Q")))] - "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCUmode)" "@ clgr\t%0,%1 clgfi\t%0,%1 @@ -1540,7 +1504,7 @@ (match_operand:SPACESHIP_INT 1 "register_operand") (match_operand:SPACESHIP_INT 2 "register_operand") (match_operand:SI 3 "const_int_operand")] - "TARGET_Z13 && TARGET_64BIT" + "TARGET_Z13" "s390_expand_int_spaceship (operands[0], operands[1], operands[2], operands[3]); DONE;") (define_mode_iterator SPACESHIP_BFP [TF DF SF]) @@ -1549,7 +1513,7 @@ (match_operand:SPACESHIP_BFP 1 "register_operand") (match_operand:SPACESHIP_BFP 2 "register_operand") (match_operand:SI 3 "const_int_operand")] - "TARGET_Z13 && TARGET_64BIT && TARGET_HARD_FLOAT" + "TARGET_Z13 && TARGET_HARD_FLOAT" "s390_expand_fp_spaceship (operands[0], operands[1], operands[2], operands[3]); DONE;") @@ -1665,8 +1629,8 @@ (define_insn "*cmp_and_br_signed_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_signed_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "nonmemory_operand" "d,C")]) + [(match_operand:DSI 1 "register_operand" "d,d") + (match_operand:DSI 2 "nonmemory_operand" "d,C")]) (label_ref (match_operand 3 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] @@ -1693,8 +1657,8 @@ (define_insn "*cmp_and_br_unsigned_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "nonmemory_operand" "d,I")]) + [(match_operand:DSI 1 "register_operand" "d,d") + (match_operand:DSI 2 "nonmemory_operand" "d,I")]) (label_ref (match_operand 3 "" "")) (pc))) (clobber (reg:CC CC_REGNUM))] @@ -1723,8 +1687,8 @@ (define_insn "*icmp_and_br_signed_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_signed_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "nonmemory_operand" "d,C")]) + [(match_operand:DSI 1 "register_operand" "d,d") + (match_operand:DSI 2 "nonmemory_operand" "d,C")]) (pc) (label_ref (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM))] @@ -1751,8 +1715,8 @@ (define_insn "*icmp_and_br_unsigned_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "nonmemory_operand" "d,I")]) + [(match_operand:DSI 1 "register_operand" "d,d") + (match_operand:DSI 2 "nonmemory_operand" "d,I")]) (pc) (label_ref (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM))] @@ -1787,7 +1751,7 @@ (define_insn "*movti_bigconst" [(set (match_operand:TI 0 "register_operand" "=d") (match_operand:TI 1 "reload_const_wide_int_operand" ""))] - "TARGET_ZARCH" + "" "#") ; FIXME: More constants are possible by enabling jxx, jyy constraints @@ -1795,7 +1759,7 @@ (define_insn "movti" [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v, v, v, v,v,d,v,R,d, d, d, d, d,o") (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,jyy,jxx,jzz,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] - "TARGET_ZARCH" + "" "@ lmg\t%0,%N0,%S1 stmg\t%1,%N1,%S0 @@ -1822,7 +1786,7 @@ (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") (match_operand:TI 1 "general_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && s390_split_ok_p (operands[0], operands[1], TImode, 0)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1836,7 +1800,7 @@ (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") (match_operand:TI 1 "general_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && s390_split_ok_p (operands[0], operands[1], TImode, 1)" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1853,7 +1817,7 @@ (define_split [(set (match_operand:TI 0 "register_operand" "") (match_operand:TI 1 "memory_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && !VECTOR_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -1892,30 +1856,30 @@ ; Unfortunately there is no such variant for QI, TI and FP mode moves. ; These patterns are also used for unaligned SI and DI accesses. -(define_expand "reload<ALL:mode><P:mode>_tomem_z10" +(define_expand "reload<ALL:mode>di_tomem_z10" [(parallel [(match_operand:ALL 0 "memory_operand" "") (match_operand:ALL 1 "register_operand" "=d") - (match_operand:P 2 "register_operand" "=&a")])] + (match_operand:DI 2 "register_operand" "=&a")])] "TARGET_Z10" { s390_reload_symref_address (operands[1], operands[0], operands[2], 1); DONE; }) -(define_expand "reload<ALL:mode><P:mode>_toreg_z10" +(define_expand "reload<ALL:mode>di_toreg_z10" [(parallel [(match_operand:ALL 0 "register_operand" "=d") (match_operand:ALL 1 "memory_operand" "") - (match_operand:P 2 "register_operand" "=a")])] + (match_operand:DI 2 "register_operand" "=a")])] "TARGET_Z10" { s390_reload_symref_address (operands[0], operands[1], operands[2], 0); DONE; }) -(define_expand "reload<P:mode>_larl_odd_addend_z10" - [(parallel [(match_operand:P 0 "register_operand" "=d") - (match_operand:P 1 "larl_operand" "") - (match_operand:P 2 "register_operand" "=a")])] +(define_expand "reloaddi_larl_odd_addend_z10" + [(parallel [(match_operand:DI 0 "register_operand" "=d") + (match_operand:DI 1 "larl_operand" "") + (match_operand:DI 2 "register_operand" "=a")])] "TARGET_Z10" { s390_reload_larl_operand (operands[0], operands[1], operands[2]); @@ -1924,10 +1888,10 @@ ; Handles loading a PLUS (load address) expression -(define_expand "reload<mode>_plus" - [(parallel [(match_operand:P 0 "register_operand" "=a") - (match_operand:P 1 "s390_plus_operand" "") - (match_operand:P 2 "register_operand" "=&a")])] +(define_expand "reloaddi_plus" + [(parallel [(match_operand:DI 0 "register_operand" "=a") + (match_operand:DI 1 "s390_plus_operand" "") + (match_operand:DI 2 "register_operand" "=&a")])] "" { s390_expand_plus_operand (operands[0], operands[1], operands[2]); @@ -1943,10 +1907,10 @@ ; - non-offsetable memory accesses for multiword moves ; - full vector reg moves with long displacements -(define_expand "reload<mode>_la_in" - [(parallel [(match_operand 0 "register_operand" "") - (match_operand 1 "" "") - (match_operand:P 2 "register_operand" "=&a")])] +(define_expand "reloaddi_la_in" + [(parallel [(match_operand 0 "register_operand" "") + (match_operand 1 "" "") + (match_operand:DI 2 "register_operand" "=&a")])] "" { gcc_assert (MEM_P (operands[1])); @@ -1956,10 +1920,10 @@ DONE; }) -(define_expand "reload<mode>_la_out" - [(parallel [(match_operand 0 "" "") - (match_operand 1 "register_operand" "") - (match_operand:P 2 "register_operand" "=&a")])] +(define_expand "reloaddi_la_out" + [(parallel [(match_operand 0 "" "") + (match_operand 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "=&a")])] "" { gcc_assert (MEM_P (operands[0])); @@ -1969,10 +1933,10 @@ DONE; }) -(define_expand "reload<mode>_PIC_addr" - [(parallel [(match_operand 0 "register_operand" "=d") - (match_operand 1 "larl_operand" "") - (match_operand:P 2 "register_operand" "=a")])] +(define_expand "reloaddi_PIC_addr" + [(parallel [(match_operand 0 "register_operand" "=d") + (match_operand 1 "larl_operand" "") + (match_operand:DI 2 "register_operand" "=a")])] "" { rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); @@ -1989,11 +1953,10 @@ "" { /* Handle symbolic constants. */ - if (TARGET_64BIT - && (SYMBOLIC_CONST (operands[1]) - || (GET_CODE (operands[1]) == PLUS - && XEXP (operands[1], 0) == pic_offset_table_rtx - && SYMBOLIC_CONST (XEXP (operands[1], 1))))) + if (SYMBOLIC_CONST (operands[1]) + || (GET_CODE (operands[1]) == PLUS + && XEXP (operands[1], 0) == pic_offset_table_rtx + && SYMBOLIC_CONST (XEXP (operands[1], 1)))) emit_symbolic_move (operands); }) @@ -2002,7 +1965,7 @@ "=d, d, d, d, d, d, d, d,f,d,!*f,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") (match_operand:DI 1 "general_operand" " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,j00,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] - "TARGET_ZARCH" + "" "@ lghi\t%0,%h1 llihh\t%0,%i1 @@ -2092,7 +2055,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "a")) (const_int LXAMODEITER)))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "lxa<lxamode>\t%0,0(%1,0)" [(set_attr "op_type" "RXY")]) @@ -2102,7 +2065,7 @@ (ashift:DI (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "const_int_operand"))) (const_int LXAMODEITER)))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "lxa<lxamode>\t%0,%2(%1,0)" [(set_attr "op_type" "RXY")]) @@ -2112,7 +2075,7 @@ (plus:DI (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "a")) (const_int LXAMODEITER)) (match_operand:DI 2 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "lxa<lxamode>\t%0,0(%1,%2)" [(set_attr "op_type" "RXY")]) @@ -2123,7 +2086,7 @@ (match_operand:SI 2 "const_int_operand"))) (const_int LXAMODEITER)) (match_operand:DI 3 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "lxa<lxamode>\t%0,%2(%1,%3)" [(set_attr "op_type" "RXY")]) @@ -2132,7 +2095,7 @@ (plus:DI (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "const_int_operand"))) (match_operand:DI 3 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "lxab\t%0,%2(%1,%3)" [(set_attr "op_type" "RXY")]) @@ -2149,7 +2112,7 @@ 0) (const_int LXAMODEITER)) (const_int <LLXAMASK>)))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "llxa<lxamode>\t%0,%2(%1,0)" [(set_attr "op_type" "RXY")]) @@ -2160,7 +2123,7 @@ (const_int LXAMODEITER)) (const_int <LLXAMASK>)) (match_operand:DI 2 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "llxa<lxamode>\t%0,0(%1,%2)" [(set_attr "op_type" "RXY")]) @@ -2173,7 +2136,7 @@ (const_int LXAMODEITER)) (const_int <LLXAMASK>)) (match_operand:DI 3 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "llxa<lxamode>\t%0,%2(%1,%3)" [(set_attr "op_type" "RXY")]) @@ -2182,29 +2145,20 @@ (plus:DI (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a") (match_operand:SI 2 "const_int_operand"))) (match_operand:DI 3 "register_operand" "a")))] - "TARGET_Z17 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" + "TARGET_Z17 && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF" "llxab\t%0,%2(%1,%3)" [(set_attr "op_type" "RXY")]) ; Splitters for loading TLS pointer from UNSPEC_GET_TP. -; UNSPEC_GET_TP is used instead of %a0:P, since the latter is a hard register, +; UNSPEC_GET_TP is used instead of %a0:DI, since the latter is a hard register, ; and those are not handled by Partial Redundancy Elimination (gcse.cc), which ; results in generation of redundant thread pointer loads. -(define_insn_and_split "*get_tp_31" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "register_operand" "t")] - UNSPEC_GET_TP))] - "" - "#" - "&& reload_completed" - [(set (match_dup 0) (match_dup 1))]) - (define_insn_and_split "*get_tp_64" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "t")] UNSPEC_GET_TP))] - "TARGET_ZARCH" + "" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 3)) @@ -2218,7 +2172,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed + "ACCESS_REG_P (operands[0]) && reload_completed && dead_or_set_p (insn, operands[1])" [(set (match_dup 3) (match_dup 2)) (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) @@ -2229,7 +2183,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed + "ACCESS_REG_P (operands[0]) && reload_completed && !dead_or_set_p (insn, operands[1])" [(set (match_dup 3) (match_dup 2)) (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) @@ -2238,95 +2192,10 @@ "operands[2] = gen_lowpart (SImode, operands[1]); s390_split_access_reg (operands[0], &operands[3], &operands[4]);") -(define_insn "*movdi_31" - [(set (match_operand:DI 0 "nonimmediate_operand" - "=d,d,Q,S,d ,o,!*f,!*f,!*f,!*f,!R,!T,d") - (match_operand:DI 1 "general_operand" - " Q,S,d,d,dPT,d, *f, R, T,j00,*f,*f,b"))] - "!TARGET_ZARCH" - "@ - lm\t%0,%N0,%S1 - lmy\t%0,%N0,%S1 - stm\t%1,%N1,%S0 - stmy\t%1,%N1,%S0 - # - # - ldr\t%0,%1 - ld\t%0,%1 - ldy\t%0,%1 - lzdr\t%0 - std\t%1,%0 - stdy\t%1,%0 - #" - [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RRE,RX,RXY,*") - (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fsimpdf,fstoredf,fstoredf,*") - (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,*,longdisp,z10")]) - -; For a load from a symbol ref we can use one of the target registers -; together with larl to load the address. -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "memory_operand" ""))] - "!TARGET_ZARCH && reload_completed && TARGET_Z10 - && larl_operand (XEXP (operands[1], 0), SImode)" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 0) (match_dup 1))] -{ - operands[2] = operand_subword (operands[0], 1, 0, DImode); - operands[3] = XEXP (operands[1], 0); - operands[1] = replace_equiv_address (operands[1], operands[2]); -}) - -(define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !s_operand (operands[0], DImode) - && !s_operand (operands[1], DImode) - && s390_split_ok_p (operands[0], operands[1], DImode, 0)" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] -{ - operands[2] = operand_subword (operands[0], 0, 0, DImode); - operands[3] = operand_subword (operands[0], 1, 0, DImode); - operands[4] = operand_subword (operands[1], 0, 0, DImode); - operands[5] = operand_subword (operands[1], 1, 0, DImode); -}) - -(define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !s_operand (operands[0], DImode) - && !s_operand (operands[1], DImode) - && s390_split_ok_p (operands[0], operands[1], DImode, 1)" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] -{ - operands[2] = operand_subword (operands[0], 1, 0, DImode); - operands[3] = operand_subword (operands[0], 0, 0, DImode); - operands[4] = operand_subword (operands[1], 1, 0, DImode); - operands[5] = operand_subword (operands[1], 0, 0, DImode); -}) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "memory_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !FP_REG_P (operands[0]) - && !s_operand (operands[1], VOIDmode)" - [(set (match_dup 0) (match_dup 1))] -{ - rtx addr = operand_subword (operands[0], 1, 0, DImode); - s390_load_address (addr, XEXP (operands[1], 0)); - operands[1] = replace_equiv_address (operands[1], addr); -}) - (define_peephole2 [(set (match_operand:DI 0 "register_operand" "") (mem:DI (match_operand 1 "address_operand" "")))] - "TARGET_ZARCH - && !FP_REG_P (operands[0]) + "!FP_REG_P (operands[0]) && GET_CODE (operands[1]) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (operands[1]) && get_pool_mode (operands[1]) == DImode @@ -2337,7 +2206,7 @@ (define_insn "*la_64" [(set (match_operand:DI 0 "register_operand" "=d,d") (match_operand:QI 1 "address_operand" "ZR,ZT"))] - "TARGET_64BIT" + "" "@ la\t%0,%a1 lay\t%0,%a1" @@ -2351,8 +2220,7 @@ [(set (match_operand:DI 0 "register_operand" "") (match_operand:QI 1 "address_operand" "")) (clobber (reg:CC CC_REGNUM))])] - "TARGET_64BIT - && preferred_la_operand_p (operands[1], const0_rtx)" + "preferred_la_operand_p (operands[1], const0_rtx)" [(set (match_dup 0) (match_dup 1))] "") @@ -2364,8 +2232,7 @@ (plus:DI (match_dup 0) (match_operand:DI 2 "nonmemory_operand" ""))) (clobber (reg:CC CC_REGNUM))])] - "TARGET_64BIT - && !reg_overlap_mentioned_p (operands[0], operands[2]) + "!reg_overlap_mentioned_p (operands[0], operands[2]) && preferred_la_operand_p (operands[1], operands[2])" [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] "") @@ -2376,8 +2243,7 @@ (define_peephole2 [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "memory_operand" ""))] - "TARGET_64BIT - && TARGET_EXTIMM + "TARGET_EXTIMM && GENERAL_REG_P (operands[0]) && s390_const_int_pool_entry_p (operands[1], nullptr) && peep2_reg_dead_p (1, gen_rtx_REG (CCmode, CC_REGNUM))" @@ -2407,37 +2273,12 @@ ; movsi instruction pattern(s). ; -(define_expand "movsi" - [(set (match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "general_operand" ""))] - "" -{ - /* Handle symbolic constants. */ - if (!TARGET_64BIT - && (SYMBOLIC_CONST (operands[1]) - || (GET_CODE (operands[1]) == PLUS - && XEXP (operands[1], 0) == pic_offset_table_rtx - && SYMBOLIC_CONST (XEXP(operands[1], 1))))) - emit_symbolic_move (operands); -}) - -(define_insn "*movsi_larl" - [(set (match_operand:SI 0 "register_operand" "=d") - (match_operand:SI 1 "larl_operand" "X"))] - "!TARGET_64BIT - && !FP_REG_P (operands[0])" - "larl\t%0,%1" - [(set_attr "op_type" "RIL") - (set_attr "type" "larl") - (set_attr "z10prop" "z10_fwd_A1") - (set_attr "relative_long" "yes")]) - -(define_insn "*movsi_zarch" +(define_insn "movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") (match_operand:SI 1 "general_operand" " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] - "TARGET_ZARCH" + "" "@ lhi\t%0,%h1 llilh\t%0,%i1 @@ -2525,31 +2366,6 @@ *,*,*,*,*,*,*,*,*,*, *,yes,*,*,*,*,*,*,*,*")]) -(define_insn "*movsi_esa" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") - (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] - "!TARGET_ZARCH" - "@ - lhi\t%0,%h1 - lr\t%0,%1 - l\t%0,%1 - st\t%1,%0 - ldr\t%0,%1 - ler\t%0,%1 - lde\t%0,%1 - le\t%0,%1 - ste\t%1,%0 - ear\t%0,%1 - sar\t%0,%1 - stam\t%1,%1,%S0 - lam\t%0,%0,%S1" - [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") - (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") - (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, - z10_super,*,*") - (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") -]) - (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") (mem:SI (match_operand 1 "address_operand" "")))] @@ -2561,82 +2377,6 @@ [(set (match_dup 0) (match_dup 2))] "operands[2] = get_pool_constant (operands[1]);") -(define_insn "*la_31" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (match_operand:QI 1 "address_operand" "ZR,ZT"))] - "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" - "@ - la\t%0,%a1 - lay\t%0,%a1" - [(set_attr "op_type" "RX,RXY") - (set_attr "type" "la") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) - -(define_peephole2 - [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:QI 1 "address_operand" "")) - (clobber (reg:CC CC_REGNUM))])] - "!TARGET_64BIT - && preferred_la_operand_p (operands[1], const0_rtx)" - [(set (match_dup 0) (match_dup 1))] - "") - -(define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")) - (parallel - [(set (match_dup 0) - (plus:SI (match_dup 0) - (match_operand:SI 2 "nonmemory_operand" ""))) - (clobber (reg:CC CC_REGNUM))])] - "!TARGET_64BIT - && !reg_overlap_mentioned_p (operands[0], operands[2]) - && preferred_la_operand_p (operands[1], operands[2])" - [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] - "") - -(define_insn "*la_31_and" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") - (const_int 2147483647)))] - "!TARGET_64BIT" - "@ - la\t%0,%a1 - lay\t%0,%a1" - [(set_attr "op_type" "RX,RXY") - (set_attr "type" "la") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) - -(define_insn_and_split "*la_31_and_cc" - [(set (match_operand:SI 0 "register_operand" "=d") - (and:SI (match_operand:QI 1 "address_operand" "p") - (const_int 2147483647))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (and:SI (match_dup 1) (const_int 2147483647)))] - "" - [(set_attr "op_type" "RX") - (set_attr "type" "la")]) - -(define_insn "force_la_31" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (match_operand:QI 1 "address_operand" "ZR,ZT")) - (use (const_int 0))] - "!TARGET_64BIT" - "@ - la\t%0,%a1 - lay\t%0,%a1" - [(set_attr "op_type" "RX") - (set_attr "type" "la") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) - ; ; movhi instruction pattern(s). ; @@ -2714,7 +2454,7 @@ { /* On z/Architecture, zero-extending from memory to register is just as fast as a QImode load. */ - if (TARGET_ZARCH && optimize && can_create_pseudo_p () + if (optimize && can_create_pseudo_p () && register_operand (operands[0], VOIDmode) && GET_CODE (operands[1]) == MEM) { @@ -2799,7 +2539,7 @@ (define_insn "movstrictsi" [(set (strict_low_part (match_operand:SI 0 "subreg_register_operand" "+d,d,d,d")) (match_operand:SI 1 "general_operand" "d,R,T,t"))] - "TARGET_ZARCH" + "" "@ lr\t%0,%1 l\t%0,%1 @@ -2823,7 +2563,7 @@ (define_insn "*mov<mode>_64" [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] - "TARGET_ZARCH" + "" "@ lzxr\t%0 lxr\t%0,%1 @@ -2837,25 +2577,12 @@ (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) -(define_insn "*mov<mode>_31" - [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") - (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] - "!TARGET_ZARCH" - "@ - lzxr\t%0 - lxr\t%0,%1 - # - #" - [(set_attr "op_type" "RRE,RRE,*,*") - (set_attr "type" "fsimptf,fsimptf,*,*") - (set_attr "cpu_facility" "z196,*,*,*")]) - ; TFmode in GPRs splitters (define_split [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") (match_operand:TD_TF 1 "general_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && !s_operand (operands[0], <MODE>mode) && !s_operand (operands[1], <MODE>mode) && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" @@ -2871,7 +2598,7 @@ (define_split [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") (match_operand:TD_TF 1 "general_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && !s_operand (operands[0], <MODE>mode) && !s_operand (operands[1], <MODE>mode) && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" @@ -2887,7 +2614,7 @@ (define_split [(set (match_operand:TD_TF 0 "register_operand" "") (match_operand:TD_TF 1 "memory_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && GENERAL_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -2979,7 +2706,7 @@ (define_insn "*mov<mode>_64" [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] - "TARGET_ZARCH" + "" "@ lzdr\t%0 ldr\t%0,%1 @@ -3000,75 +2727,6 @@ (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) -(define_insn "*mov<mode>_31" - [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,f,R,T,d,d,Q,S, d,o") - (match_operand:DD_DF 1 "general_operand" - " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] - "!TARGET_ZARCH" - "@ - lzdr\t%0 - ldr\t%0,%1 - ld\t%0,%1 - ldy\t%0,%1 - std\t%1,%0 - stdy\t%1,%0 - lm\t%0,%N0,%S1 - lmy\t%0,%N0,%S1 - stm\t%1,%N1,%S0 - stmy\t%1,%N1,%S0 - # - #" - [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") - (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, - fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") - (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) - -(define_split - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") - (match_operand:DD_DF 1 "general_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !s_operand (operands[0], <MODE>mode) - && !s_operand (operands[1], <MODE>mode) - && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] -{ - operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); - operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); - operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); - operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); -}) - -(define_split - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") - (match_operand:DD_DF 1 "general_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !s_operand (operands[0], <MODE>mode) - && !s_operand (operands[1], <MODE>mode) - && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (match_dup 5))] -{ - operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); - operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); - operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); - operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); -}) - -(define_split - [(set (match_operand:DD_DF 0 "register_operand" "") - (match_operand:DD_DF 1 "memory_operand" ""))] - "!TARGET_ZARCH && reload_completed - && !FP_REG_P (operands[0]) - && !s_operand (operands[1], VOIDmode)" - [(set (match_dup 0) (match_dup 1))] -{ - rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); - s390_load_address (addr, XEXP (operands[1], 0)); - operands[1] = replace_equiv_address (operands[1], addr); -}) - ; ; mov(sf|sd) instruction pattern(s). ; @@ -3116,7 +2774,7 @@ (define_insn "movhf" [(set (match_operand:HF 0 "nonimmediate_operand") (match_operand:HF 1 "general_operand"))] - "TARGET_64BIT" + "" {@ [ cons: =0, 1; attrs: op_type, cpu_facility ] [ v , v ; VRR , vx ] vlr\t%v0,%v1 [ v , d ; VRS , vx ] vlvgh\t%v0,%1,0 @@ -3294,7 +2952,7 @@ count = INTVAL (operands[2]); regno = REGNO (operands[0]); mode = GET_MODE (operands[0]); - if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) + if (mode != SImode && mode != DImode) FAIL; operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); @@ -3333,7 +2991,7 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:DI 1 "register_operand" "=r") (match_operand:DI 2 "s_operand" "S"))])] - "reload_completed && TARGET_ZARCH" + "reload_completed" { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); @@ -3385,7 +3043,7 @@ count = INTVAL (operands[2]); regno = REGNO (operands[1]); mode = GET_MODE (operands[1]); - if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) + if (mode != SImode && mode != DImode) FAIL; operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); @@ -3425,7 +3083,7 @@ [(match_parallel 0 "store_multiple_operation" [(set (match_operand:DI 1 "s_operand" "=S") (match_operand:DI 2 "register_operand" "r"))])] - "reload_completed && TARGET_ZARCH" + "reload_completed" { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); @@ -3481,35 +3139,35 @@ ; strlenM instruction pattern(s). ; -(define_expand "strlen<mode>" - [(match_operand:P 0 "register_operand" "") ; result +(define_expand "strlendi" + [(match_operand:DI 0 "register_operand" "") ; result (match_operand:BLK 1 "memory_operand" "") ; input string (match_operand:SI 2 "immediate_operand" "") ; search character (match_operand:SI 3 "immediate_operand" "")] ; known alignment "" { if (!TARGET_VX || operands[2] != const0_rtx) - emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], - operands[2], operands[3])); + emit_insn (gen_strlen_srstdi (operands[0], operands[1], + operands[2], operands[3])); else s390_expand_vec_strlen (operands[0], operands[1], operands[3]); DONE; }) -(define_expand "strlen_srst<mode>" +(define_expand "strlen_srstdi" [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) (parallel [(set (match_dup 4) - (unspec:P [(const_int 0) + (unspec:DI [(const_int 0) (match_operand:BLK 1 "memory_operand" "") (reg:SI 0) (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (scratch:P)) + (clobber (scratch:DI)) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_operand:P 0 "register_operand" "") - (minus:P (match_dup 4) (match_dup 5))) + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_dup 4) (match_dup 5))) (clobber (reg:CC CC_REGNUM))])] "" { @@ -3519,13 +3177,13 @@ operands[1] = replace_equiv_address (operands[1], operands[5]); }) -(define_insn "*strlen<mode>" - [(set (match_operand:P 0 "register_operand" "=a") - (unspec:P [(match_operand:P 2 "general_operand" "0") - (mem:BLK (match_operand:P 3 "register_operand" "1")) +(define_insn "*strlendi" + [(set (match_operand:DI 0 "register_operand" "=a") + (unspec:DI [(match_operand:DI 2 "general_operand" "0") + (mem:BLK (match_operand:DI 3 "register_operand" "1")) (reg:SI 0) (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) - (clobber (match_scratch:P 1 "=a")) + (clobber (match_scratch:DI 1 "=a")) (clobber (reg:CC CC_REGNUM))] "" "srst\t%0,%1\;jo\t.-4" @@ -3566,12 +3224,12 @@ operands[4] = addr2; }) -(define_insn "*cmpstr<mode>" - [(clobber (match_operand:P 0 "register_operand" "=d")) - (clobber (match_operand:P 1 "register_operand" "=d")) +(define_insn "*cmpstrdi" + [(clobber (match_operand:DI 0 "register_operand" "=d")) + (clobber (match_operand:DI 1 "register_operand" "=d")) (set (reg:CCU CC_REGNUM) - (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) - (mem:BLK (match_operand:P 3 "register_operand" "1")))) + (compare:CCU (mem:BLK (match_operand:DI 2 "register_operand" "0")) + (mem:BLK (match_operand:DI 3 "register_operand" "1")))) (use (reg:SI 0))] "" "clst\t%0,%1\;jo\t.-4" @@ -3583,28 +3241,15 @@ ; (define_expand "movstr" - [(match_operand 0 "register_operand" "") - (match_operand 1 "memory_operand" "") - (match_operand 2 "memory_operand" "")] - "" -{ - if (TARGET_64BIT) - emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); - else - emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "movstr<P:mode>" [(set (reg:SI 0) (const_int 0)) (parallel [(clobber (match_dup 3)) (set (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "")) - (set (match_operand:P 0 "register_operand" "") - (unspec:P [(match_dup 1) - (match_dup 2) - (reg:SI 0)] UNSPEC_MVST)) + (set (match_operand:DI 0 "register_operand" "") + (unspec:DI [(match_dup 1) + (match_dup 2) + (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))])] "" { @@ -3627,13 +3272,13 @@ }) (define_insn "*movstr" - [(clobber (match_operand:P 2 "register_operand" "=d")) - (set (mem:BLK (match_operand:P 1 "register_operand" "0")) - (mem:BLK (match_operand:P 3 "register_operand" "2"))) - (set (match_operand:P 0 "register_operand" "=d") - (unspec:P [(mem:BLK (match_dup 1)) - (mem:BLK (match_dup 3)) - (reg:SI 0)] UNSPEC_MVST)) + [(clobber (match_operand:DI 2 "register_operand" "=d")) + (set (mem:BLK (match_operand:DI 1 "register_operand" "0")) + (mem:BLK (match_operand:DI 3 "register_operand" "2"))) + (set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(mem:BLK (match_dup 1)) + (mem:BLK (match_dup 3)) + (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))] "" "mvst\t%1,%2\;jo\t.-4" @@ -3648,7 +3293,7 @@ (define_expand "cpymem<mode>" [(set (match_operand:BLK 0 "memory_operand" "") ; destination (match_operand:BLK 1 "memory_operand" "")) ; source - (use (match_operand:GPR 2 "general_operand" "")) ; size + (use (match_operand:DSI 2 "general_operand" "")) ; size (match_operand 3 "") ; align (match_operand 4 "") ; expected align (match_operand 5 "") ; expected size @@ -3680,11 +3325,11 @@ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) (use (match_operand 3 "immediate_operand" "X,R,X,X")) - (clobber (match_scratch:P 4 "=X,X,X,&a"))] + (clobber (match_scratch:DI 4 "=X,X,X,&a"))] "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" "#" [(set_attr "type" "cs") - (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -3754,12 +3399,10 @@ (clobber (reg:CC CC_REGNUM))])] "" { - machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; - machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dreg_mode); - rtx reg1 = gen_reg_rtx (dreg_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); - rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); + rtx reg0 = gen_reg_rtx (TImode); + rtx reg1 = gen_reg_rtx (TImode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (DImode, reg0)); + rtx addr1 = gen_lowpart (Pmode, gen_highpart (DImode, reg1)); rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); @@ -3778,27 +3421,14 @@ }) (define_insn "*cpymem_long" - [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) - (clobber (match_operand:<DBL> 1 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) - (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) - (use (match_dup 2)) - (use (match_dup 3)) - (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT || !TARGET_ZARCH" - "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*cpymem_long_31z" [(clobber (match_operand:TI 0 "register_operand" "=d")) (clobber (match_operand:TI 1 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) - (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) + (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) + (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) (use (match_dup 2)) (use (match_dup 3)) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_ZARCH" + "" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -3806,7 +3436,7 @@ (define_expand "movmem<mode>" [(set (match_operand:BLK 0 "memory_operand") ; destination (match_operand:BLK 1 "memory_operand")) ; source - (use (match_operand:GPR 2 "general_operand")) ; size + (use (match_operand:DSI 2 "general_operand")) ; size (match_operand 3 "") ; align (match_operand 4 "") ; expected align (match_operand 5 "") ; expected size @@ -3872,7 +3502,7 @@ (define_expand "signbithf2" [(match_operand:SI 0 "register_operand") (match_operand:HF 1 "nonimmediate_operand")] - "TARGET_HARD_FLOAT && TARGET_Z10 && TARGET_64BIT" + "TARGET_HARD_FLOAT && TARGET_Z10" { if (TARGET_VX) { @@ -3894,12 +3524,12 @@ (match_operand:SIGNBIT_SINGLE 1 "nonimmediate_operand")] "" { - if (TARGET_VX && TARGET_64BIT) + if (TARGET_VX) { emit_insn (gen_rtx_SET (operands[0], simplify_gen_subreg (SImode, operands[1], <MODE>mode, 0))); emit_insn (gen_rtx_SET (operands[0], gen_rtx_LSHIFTRT (SImode, operands[0], GEN_INT (31)))); } - else if (TARGET_Z10 && TARGET_64BIT) + else if (TARGET_Z10) emit_insn (gen_signbit<mode>2_z10 (operands[0], operands[1])); else emit_insn (gen_signbit_tdc<mode>2 (operands[0], force_reg (<MODE>mode, operands[1]))); @@ -3914,14 +3544,14 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SIGNBIT_HALF_SINGLE 1 "nonimmediate_operand" "fRT")] UNSPEC_SIGNBIT))] - "TARGET_Z10 && TARGET_64BIT" + "TARGET_Z10" "#") (define_split [(set (match_operand:SI 0 "register_operand") (unspec:SI [(match_operand:SIGNBIT_HALF_SINGLE 1 "register_operand")] UNSPEC_SIGNBIT))] - "TARGET_Z10 && TARGET_64BIT && reload_completed" + "TARGET_Z10 && reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 63)))] { @@ -3933,7 +3563,7 @@ [(set (match_operand:SI 0 "register_operand") (unspec:SI [(match_operand:SIGNBIT_HALF_SINGLE 1 "memory_operand")] UNSPEC_SIGNBIT))] - "TARGET_Z10 && TARGET_64BIT && reload_completed" + "TARGET_Z10 && reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))] { @@ -3959,7 +3589,7 @@ (match_operand:SIGNBIT_DBL_TETRA 1 "nonimmediate_operand")] "" { - if (TARGET_Z10 && TARGET_64BIT) + if (TARGET_Z10) { rtx reg_di = gen_reg_rtx (DImode); if (<MODE>mode == TFmode || <MODE>mode == TDmode) @@ -4018,7 +3648,7 @@ (define_expand "setmem<mode>" [(set (match_operand:BLK 0 "memory_operand" "") ; destination (match_operand:QI 2 "general_operand" "")) ; value - (use (match_operand:GPR 1 "general_operand" "")) ; size + (use (match_operand:DSI 1 "general_operand" "")) ; size (match_operand 3 "") ; align (match_operand 4 "") ; expected align (match_operand 5 "") ; expected size @@ -4046,12 +3676,12 @@ (const_int 0)) (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) (use (match_operand 2 "immediate_operand" "X,R,X,X")) - (clobber (match_scratch:P 3 "=X,X,X,&a")) + (clobber (match_scratch:DI 3 "=X,X,X,&a")) (clobber (reg:CC CC_REGNUM))] "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" "#" [(set_attr "type" "cs") - (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -4118,21 +3748,19 @@ ; Initialize a block of arbitrary length with (operands[2] % 256). -(define_expand "setmem_long_<P:mode>" +(define_expand "setmem_long_di" [(parallel [(clobber (match_dup 1)) (set (match_operand:BLK 0 "memory_operand" "") - (unspec:BLK [(match_operand:P 2 "setmem_operand" "") - (match_dup 4)] UNSPEC_REPLICATE_BYTE)) + (unspec:BLK [(match_operand:DI 2 "setmem_operand" "") + (match_dup 4)] UNSPEC_REPLICATE_BYTE)) (use (match_dup 3)) (clobber (reg:CC CC_REGNUM))])] "" { - machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; - machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dreg_mode); - rtx reg1 = gen_reg_rtx (dreg_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); + rtx reg0 = gen_reg_rtx (TImode); + rtx reg1 = gen_reg_rtx (TImode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (DImode, reg0)); rtx len0 = gen_lowpart (Pmode, reg0); emit_clobber (reg0); @@ -4147,57 +3775,28 @@ operands[4] = gen_lowpart (Pmode, operands[1]); }) -; Patterns for 31 bit + Esa and 64 bit + Zarch. - (define_insn "*setmem_long" - [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) - (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") - (subreg:P (match_dup 3) <modesize>)] - UNSPEC_REPLICATE_BYTE)) - (use (match_operand:<DBL> 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "TARGET_64BIT || !TARGET_ZARCH" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*setmem_long_and" - [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) - (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) - (subreg:P (match_dup 3) <modesize>)] - UNSPEC_REPLICATE_BYTE)) - (use (match_operand:<DBL> 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "(TARGET_64BIT || !TARGET_ZARCH)" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets -; of the SImode subregs. - -(define_insn "*setmem_long_31z" [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) - (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") - (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) + (set (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "0") 0)) + (unspec:BLK [(match_operand:DI 2 "setmem_operand" "Y") + (subreg:DI (match_dup 3) <modesize>)] + UNSPEC_REPLICATE_BYTE)) (use (match_operand:TI 1 "register_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "!TARGET_64BIT && TARGET_ZARCH" + "" "mvcle\t%0,%1,%Y2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) -(define_insn "*setmem_long_and_31z" +(define_insn "*setmem_long_and" [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) - (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) - (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) + (set (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "0") 0)) + (unspec:BLK [(zero_extend:DI (match_operand:QI 2 "setmem_operand" "Y")) + (subreg:DI (match_dup 3) <modesize>)] + UNSPEC_REPLICATE_BYTE)) (use (match_operand:TI 1 "register_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "(!TARGET_64BIT && TARGET_ZARCH)" + "" "mvcle\t%0,%1,%Y2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) @@ -4241,11 +3840,11 @@ (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) (use (match_operand 3 "immediate_operand" "X,R,X,X")) - (clobber (match_scratch:P 4 "=X,X,X,&a"))] + (clobber (match_scratch:DI 4 "=X,X,X,&a"))] "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" "#" [(set_attr "type" "cs") - (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) + (set_attr "cpu_facility" "*,*,z10,*")]) (define_split [(set (reg:CCU CC_REGNUM) @@ -4319,12 +3918,10 @@ (use (match_dup 3))])] "" { - machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; - machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; - rtx reg0 = gen_reg_rtx (dreg_mode); - rtx reg1 = gen_reg_rtx (dreg_mode); - rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); - rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); + rtx reg0 = gen_reg_rtx (TImode); + rtx reg1 = gen_reg_rtx (TImode); + rtx addr0 = gen_lowpart (Pmode, gen_highpart (DImode, reg0)); + rtx addr1 = gen_lowpart (Pmode, gen_highpart (DImode, reg1)); rtx len0 = gen_lowpart (Pmode, reg0); rtx len1 = gen_lowpart (Pmode, reg1); @@ -4343,31 +3940,17 @@ }) (define_insn "*cmpmem_long" - [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) - (clobber (match_operand:<DBL> 1 "register_operand" "=d")) - (set (reg:CCU CC_REGNUM) - (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) - (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) - (use (match_dup 2)) - (use (match_dup 3))] - "TARGET_64BIT || !TARGET_ZARCH" - "clcle\t%0,%1,0\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - -(define_insn "*cmpmem_long_31z" [(clobber (match_operand:TI 0 "register_operand" "=d")) (clobber (match_operand:TI 1 "register_operand" "=d")) (set (reg:CCU CC_REGNUM) - (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) - (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) + (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) + (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) (use (match_dup 2)) (use (match_dup 3))] - "!TARGET_64BIT && TARGET_ZARCH" + "" "clcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) ; Convert CCUmode condition code to integer. ; Result is zero if EQ, positive if LTU, negative if GTU. @@ -4410,7 +3993,7 @@ (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_STRCMPCC_TO_INT))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) @@ -4427,7 +4010,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] - "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCSmode)" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) @@ -4463,24 +4046,11 @@ (unspec:DI [(match_operand:BLK 1 "s_operand" "S") (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "icmh\t%0,%2,%S1" [(set_attr "op_type" "RSY") (set_attr "z10prop" "z10_super")]) -(define_insn "*sethighpartdi_31" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") - (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "@ - icm\t%0,%2,%S1 - icmy\t%0,%2,%S1" - [(set_attr "op_type" "RS,RSY") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) - ; ; extv instruction patterns ; @@ -4513,9 +4083,9 @@ }) (define_insn "*extzv<mode><clobbercc_or_nocc>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extract:GPR - (match_operand:GPR 1 "register_operand" "d") + [(set (match_operand:DSI 0 "register_operand" "=d") + (zero_extract:DSI + (match_operand:DSI 1 "register_operand" "d") (match_operand 2 "const_int_operand" "") ; size (match_operand 3 "const_int_operand" ""))) ; start ] @@ -4609,8 +4179,8 @@ (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*pre_z10_extzv<mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") + [(set (match_operand:DSI 0 "register_operand" "=d") + (zero_extract:DSI (match_operand:QI 1 "s_operand" "S") (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] @@ -4618,9 +4188,9 @@ "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) + [(set (match_dup 0) (unspec:DSI [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))]) - (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] + (set (match_dup 0) (lshiftrt:DSI (match_dup 0) (match_dup 2)))] { int bitsize = INTVAL (operands[2]); int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ @@ -4629,13 +4199,13 @@ operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], size); - operands[2] = GEN_INT (<GPR:bitsize> - bitsize); + operands[2] = GEN_INT (<DSI:bitsize> - bitsize); operands[3] = GEN_INT (mask); }) (define_insn_and_split "*pre_z10_extv<mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") + [(set (match_operand:DSI 0 "register_operand" "=d") + (sign_extract:DSI (match_operand:QI 1 "s_operand" "S") (match_operand 2 "nonzero_shift_count_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] @@ -4643,10 +4213,10 @@ "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) + [(set (match_dup 0) (unspec:DSI [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) + [(set (match_dup 0) (ashiftrt:DSI (match_dup 0) (match_dup 2))) (clobber (reg:CC CC_REGNUM))])] { int bitsize = INTVAL (operands[2]); @@ -4656,7 +4226,7 @@ operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], size); - operands[2] = GEN_INT (<GPR:bitsize> - bitsize); + operands[2] = GEN_INT (<DSI:bitsize> - bitsize); operands[3] = GEN_INT (mask); }) @@ -4681,10 +4251,10 @@ ; the location operand isn't word mode. However, we do this in the ; back-end when generating atomic operations. See s390_two_part_insv. (define_insn "*insv<mode><clobbercc_or_nocc>" - [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") + [(set (zero_extract:DSI (match_operand:DSI 0 "nonimmediate_operand" "+d") (match_operand 1 "const_int_operand" "I") ; size (match_operand 2 "const_int_operand" "I")) ; pos - (match_operand:GPR 3 "nonimmediate_operand" "d"))] + (match_operand:DSI 3 "nonimmediate_operand" "d"))] "<z10_or_zEC12_cond> && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), GET_MODE_BITSIZE (<MODE>mode)) @@ -4696,11 +4266,11 @@ ; and op1 with a mask being 1 for the selected bits and 0 for the rest ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") - (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") - (match_operand:GPR 2 "contiguous_bitmask_operand" "")) - (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") - (match_operand:GPR 4 "const_int_operand" ""))))] + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d,d") + (ior:DSI (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "d,0") + (match_operand:DSI 2 "contiguous_bitmask_operand" "")) + (and:DSI (match_operand:DSI 3 "nonimmediate_operand" "0,d") + (match_operand:DSI 4 "const_int_operand" ""))))] "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" "@ <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 @@ -4750,11 +4320,11 @@ ; Implement appending Y on the left of S bits of X ; x = (y << s) | (x & ((1 << s) - 1)) (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") - (match_operand:GPR 2 "immediate_operand" "")) - (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") - (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (ior:DSI (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "0") + (match_operand:DSI 2 "immediate_operand" "")) + (ashift:DSI (match_operand:DSI 3 "nonimmediate_operand" "d") + (match_operand:DSI 4 "nonzero_shift_count_operand" ""))))] "<z10_or_zEC12_cond> && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1" "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" @@ -4763,13 +4333,13 @@ ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ior:GPR (and:GPR - (match_operand:GPR 1 "register_operand" "0") - (match_operand:GPR 2 "const_int_operand" "")) - (lshiftrt:GPR - (match_operand:GPR 3 "register_operand" "d") - (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] + [(set (match_operand:DSI 0 "register_operand" "=d") + (ior:DSI (and:DSI + (match_operand:DSI 1 "register_operand" "0") + (match_operand:DSI 2 "const_int_operand" "")) + (lshiftrt:DSI + (match_operand:DSI 3 "register_operand" "d") + (match_operand:DSI 4 "nonzero_shift_count_operand" ""))))] "<z10_or_zEC12_cond> && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" @@ -4825,17 +4395,17 @@ ; -> z = y >> d; z = risbg; (define_split - [(set (match_operand:GPR 0 "nonimmediate_operand" "") - (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") - (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] + [(set (match_operand:DSI 0 "nonimmediate_operand" "") + (ior:DSI (lshiftrt:DSI (match_operand:DSI 1 "nonimmediate_operand" "") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (ashift:DSI (match_operand:DSI 3 "nonimmediate_operand" "") + (match_operand:DSI 4 "nonzero_shift_count_operand" ""))))] "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" [(set (match_dup 6) - (lshiftrt:GPR (match_dup 1) (match_dup 2))) + (lshiftrt:DSI (match_dup 1) (match_dup 2))) (set (match_dup 0) - (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) - (ashift:GPR (match_dup 3) (match_dup 4))))] + (ior:DSI (and:DSI (match_dup 6) (match_dup 5)) + (ashift:DSI (match_dup 3) (match_dup 4))))] { operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); if (reg_overlap_mentioned_p (operands[0], operands[3])) @@ -4850,19 +4420,19 @@ (define_split [(parallel - [(set (match_operand:GPR 0 "nonimmediate_operand" "") - (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") - (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "") + (ior:DSI (lshiftrt:DSI (match_operand:DSI 1 "nonimmediate_operand" "") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (ashift:DSI (match_operand:DSI 3 "nonimmediate_operand" "") + (match_operand:DSI 4 "nonzero_shift_count_operand" "")))) (clobber (reg:CC CC_REGNUM))])] "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" [(set (match_dup 6) - (lshiftrt:GPR (match_dup 1) (match_dup 2))) + (lshiftrt:DSI (match_dup 1) (match_dup 2))) (parallel [(set (match_dup 0) - (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) - (ashift:GPR (match_dup 3) (match_dup 4)))) + (ior:DSI (and:DSI (match_dup 6) (match_dup 5)) + (ashift:DSI (match_dup 3) (match_dup 4)))) (clobber (reg:CC CC_REGNUM))])] { operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); @@ -4878,11 +4448,11 @@ ; rosbg, rxsbg (define_insn "*r<noxa>sbg_<mode>_noshift" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (IXOR:GPR - (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") - (match_operand:GPR 2 "contiguous_bitmask_operand" "")) - (match_operand:GPR 3 "nonimmediate_operand" "0"))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (IXOR:DSI + (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "d") + (match_operand:DSI 2 "contiguous_bitmask_operand" "")) + (match_operand:DSI 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" @@ -4905,14 +4475,14 @@ ; rosbg, rxsbg (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (IXOR:GPR - (and:GPR - (lshiftrt:GPR - (match_operand:GPR 1 "nonimmediate_operand" "d") - (match_operand:GPR 3 "nonzero_shift_count_operand" "")) - (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) - (match_operand:GPR 4 "nonimmediate_operand" "0"))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (IXOR:DSI + (and:DSI + (lshiftrt:DSI + (match_operand:DSI 1 "nonimmediate_operand" "d") + (match_operand:DSI 3 "nonzero_shift_count_operand" "")) + (match_operand:DSI 2 "contiguous_bitmask_nowrap_operand" "")) + (match_operand:DSI 4 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), @@ -4925,14 +4495,14 @@ ; rosbg, rxsbg (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (IXOR:GPR - (and:GPR - (ashift:GPR - (match_operand:GPR 1 "nonimmediate_operand" "d") - (match_operand:GPR 3 "nonzero_shift_count_operand" "")) - (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) - (match_operand:GPR 4 "nonimmediate_operand" "0"))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (IXOR:DSI + (and:DSI + (ashift:DSI + (match_operand:DSI 1 "nonimmediate_operand" "d") + (match_operand:DSI 3 "nonzero_shift_count_operand" "")) + (match_operand:DSI 2 "contiguous_bitmask_nowrap_operand" "")) + (match_operand:DSI 4 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), @@ -4945,12 +4515,12 @@ ;; a = a ^ (b << const_int) ; rosbg, rxsbg (define_insn "*r<noxa>sbg_<mode>_sll" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (IXOR:GPR - (ashift:GPR - (match_operand:GPR 1 "nonimmediate_operand" "d") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (match_operand:GPR 3 "nonimmediate_operand" "0"))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (IXOR:DSI + (ashift:DSI + (match_operand:DSI 1 "nonimmediate_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" { @@ -4964,12 +4534,12 @@ ;; a = a ^ (b >> const_int) ; rosbg, rxsbg (define_insn "*r<noxa>sbg_<mode>_srl" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") - (IXOR:GPR - (lshiftrt:GPR - (match_operand:GPR 1 "nonimmediate_operand" "d") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (match_operand:GPR 3 "nonimmediate_operand" "0"))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d") + (IXOR:DSI + (lshiftrt:DSI + (match_operand:DSI 1 "nonimmediate_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" { @@ -5055,11 +4625,11 @@ "rnsbg\t%0,%4,%2,%2+%1-1,%3" [(set_attr "op_type" "RIE")]) -(define_insn "*insv<mode>_mem_reg" - [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") - (match_operand 1 "const_int_operand" "n,n") - (const_int 0)) - (match_operand:W 2 "register_operand" "d,d"))] +(define_insn "*insvdi_mem_reg" + [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+Q,S") + (match_operand 1 "const_int_operand" "n,n") + (const_int 0)) + (match_operand:DI 2 "register_operand" "d,d"))] "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) @@ -5081,8 +4651,7 @@ (const_int 0)) (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") (const_int 32)))] - "TARGET_ZARCH - && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) + "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) && INTVAL (operands[1]) % BITS_PER_UNIT == 0" @@ -5100,8 +4669,7 @@ (const_int 16) (match_operand 1 "const_int_operand" "n")) (match_operand:DI 2 "const_int_operand" "n"))] - "TARGET_ZARCH - && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) + "EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) < BITS_PER_WORD && INTVAL (operands[1]) % 16 == 0" @@ -5149,7 +4717,7 @@ (unspec:DI [(match_operand:DI 1 "register_operand" "d") (match_operand:DI 2 "register_operand" "d")] UNSPEC_BDEPG))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "bdepg\t%0,%1,%2" [(set_attr "op_type" "RRF")]) @@ -5162,7 +4730,7 @@ (unspec:DI [(match_operand:DI 1 "register_operand" "d") (match_operand:DI 2 "register_operand" "d")] UNSPEC_BEXTG))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "bextg\t%0,%1,%2" [(set_attr "op_type" "RRF")]) @@ -5171,25 +4739,10 @@ ; extendsidi2 instruction pattern(s). ; -(define_expand "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] - "" -{ - if (!TARGET_ZARCH) - { - emit_clobber (operands[0]); - emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); - emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); - emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); - DONE; - } -}) - -(define_insn "*extendsidi2" +(define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] - "TARGET_ZARCH" + "" "@ lgfr\t%0,%1 lgf\t%0,%1 @@ -5209,14 +4762,7 @@ (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] "" { - if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) - { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); - emit_insn (gen_extendsidi2 (operands[0], tmp)); - DONE; - } - else if (!TARGET_EXTIMM) + if (!TARGET_EXTIMM) { rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); @@ -5234,7 +4780,7 @@ (define_insn "*extendhidi2_extimm" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] - "TARGET_ZARCH && TARGET_EXTIMM" + "TARGET_EXTIMM" "@ lghr\t%0,%1 lgh\t%0,%1 @@ -5248,7 +4794,7 @@ (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] - "TARGET_ZARCH" + "" "lgh\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "z10prop" "z10_super_E1")]) @@ -5289,8 +4835,8 @@ ; lbr, lgbr, lb, lgb (define_insn "*extendqi<mode>2_extimm" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] + [(set (match_operand:DSI 0 "register_operand" "=d,d") + (sign_extend:DSI (match_operand:QI 1 "nonimmediate_operand" "d,T")))] "TARGET_EXTIMM" "@ l<g>br\t%0,%1 @@ -5300,54 +4846,40 @@ ; lb, lgb (define_insn "*extendqi<mode>2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] + [(set (match_operand:DSI 0 "register_operand" "=d") + (sign_extend:DSI (match_operand:QI 1 "memory_operand" "T")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "l<g>b\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*extendqi<mode>2_short_displ" - [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (sign_extend:DSI (match_operand:QI 1 "s_operand" "Q"))) (clobber (reg:CC CC_REGNUM))] "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) + [(set (match_dup 0) (unspec:DSI [(match_dup 1) (const_int 8)] UNSPEC_ICM)) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) + [(set (match_dup 0) (ashiftrt:DSI (match_dup 0) (match_dup 2))) (clobber (reg:CC CC_REGNUM))])] { operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], GET_MODE_SIZE (QImode)); - operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); + operands[2] = GEN_INT (<DSI:bitsize> - BITS_PER_UNIT); }) ; ; zero_extendsidi2 instruction pattern(s). ; -(define_expand "zero_extendsidi2" - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] - "" -{ - if (!TARGET_ZARCH) - { - emit_clobber (operands[0]); - emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); - emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); - DONE; - } -}) - -(define_insn "*zero_extendsidi2" +(define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b,v")))] - "TARGET_ZARCH" + "" "@ llgfr\t%0,%1 llgf\t%0,%1 @@ -5367,7 +4899,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) (const_int 2147483647)))] - "TARGET_ZARCH" + "" "llgt\t%0,%1" [(set_attr "op_type" "RXE") (set_attr "z10prop" "z10_super_E1")]) @@ -5377,7 +4909,7 @@ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "#" "&& reload_completed" [(set (match_dup 0) @@ -5389,7 +4921,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") (const_int 2147483647)))] - "TARGET_ZARCH" + "" "@ llgtr\t%0,%1 llgt\t%0,%1" @@ -5400,7 +4932,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") (const_int 2147483647)))] - "TARGET_ZARCH" + "" "@ llgtr\t%0,%1 llgt\t%0,%N1" @@ -5412,7 +4944,7 @@ (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && reload_completed" + "reload_completed" [(set (match_dup 0) (and:DSI (match_dup 1) (const_int 2147483647)))] @@ -5427,14 +4959,7 @@ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] "" { - if (!TARGET_ZARCH) - { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); - emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); - DONE; - } - else if (!TARGET_EXTIMM) + if (!TARGET_EXTIMM) { rtx bitcount = GEN_INT (64 - <HQI:bitsize>); operands[1] = gen_lowpart (DImode, operands[1]); @@ -5460,8 +4985,8 @@ ; llhrl, llghrl (define_insn "*zero_extendhi<mode>2_z10" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b,v")))] + [(set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (zero_extend:DSI (match_operand:HI 1 "nonimmediate_operand" "d,T,b,v")))] "TARGET_Z10" "@ ll<g>hr\t%0,%1 @@ -5475,9 +5000,9 @@ (set_attr "relative_long" "*,*,yes,*")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc -(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d") - (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T,v")))] +(define_insn "*zero_extend<HQI:mode><DSI:mode>2_extimm" + [(set (match_operand:DSI 0 "register_operand" "=d,d,d") + (zero_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "d,T,v")))] "TARGET_EXTIMM" "@ ll<g><hc>r\t%0,%1 @@ -5488,37 +5013,14 @@ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,*")]) ; llgh, llgc -(define_insn "*zero_extend<HQI:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] - "TARGET_ZARCH && !TARGET_EXTIMM" +(define_insn "*zero_extend<HQI:mode><DSI:mode>2" + [(set (match_operand:DSI 0 "register_operand" "=d") + (zero_extend:DSI (match_operand:HQI 1 "memory_operand" "T")))] + "!TARGET_EXTIMM" "llg<hc>\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "z10prop" "z10_fwd_A3")]) -(define_insn_and_split "*zero_extendhisi2_31" - [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (parallel - [(set (strict_low_part (match_dup 2)) (match_dup 1)) - (clobber (reg:CC CC_REGNUM))])] - "operands[2] = gen_lowpart (HImode, operands[0]);") - -(define_insn_and_split "*zero_extendqisi2_31" - [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] - "!TARGET_ZARCH" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (set (strict_low_part (match_dup 2)) (match_dup 1))] - "operands[2] = gen_lowpart (QImode, operands[0]);") - ; ; zero_extendqihi2 instruction pattern(s). ; @@ -5526,7 +5028,7 @@ (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] - "TARGET_ZARCH && !TARGET_EXTIMM" + "!TARGET_EXTIMM" { operands[1] = gen_lowpart (HImode, operands[1]); emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); @@ -5536,21 +5038,11 @@ (define_insn "*zero_extendqihi2_64" [(set (match_operand:HI 0 "register_operand" "=d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] - "TARGET_ZARCH && !TARGET_EXTIMM" + "!TARGET_EXTIMM" "llgc\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "z10prop" "z10_fwd_A3")]) -(define_insn_and_split "*zero_extendqihi2_31" - [(set (match_operand:HI 0 "register_operand" "=&d") - (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] - "!TARGET_ZARCH" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (set (strict_low_part (match_dup 2)) (match_dup 1))] - "operands[2] = gen_lowpart (QImode, operands[0]);") - ; ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander ; @@ -5558,11 +5050,11 @@ ; This is the only entry point for fixuns_trunc. It multiplexes the ; expansion to either the *_emu expanders below for pre z196 machines ; or emits the default pattern otherwise. -(define_expand "fixuns_trunc<FP:mode><GPR:mode>2<FP:tf_fpr>" +(define_expand "fixuns_trunc<FP:mode><DSI:mode>2<FP:tf_fpr>" [(parallel - [(set (match_operand:GPR 0 "register_operand" "") - (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) - (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) + [(set (match_operand:DSI 0 "register_operand" "") + (unsigned_fix:DSI (match_operand:FP 1 "register_operand" ""))) + (unspec:DSI [(match_dup 2)] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" { @@ -5570,9 +5062,9 @@ { /* We don't provide emulation for TD|DD->SI. */ if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT - && <GPR:MODE>mode == SImode) + && <DSI:MODE>mode == SImode) FAIL; - emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], + emit_insn (gen_fixuns_trunc<FP:mode><DSI:mode>2_emu (operands[0], operands[1])); DONE; } @@ -5587,11 +5079,11 @@ ; Emulate the unsigned conversion with the signed version for pre z196 ; machines. -(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" +(define_expand "fixuns_trunc<BFP:mode><DSI:mode>2_emu" [(parallel - [(set (match_operand:GPR 0 "register_operand" "") - (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) - (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) + [(set (match_operand:DSI 0 "register_operand" "") + (unsigned_fix:DSI (match_operand:BFP 1 "register_operand" ""))) + (unspec:DSI [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "!TARGET_Z196 && TARGET_HARD_FLOAT" { @@ -5601,20 +5093,20 @@ REAL_VALUE_TYPE cmp, sub; operands[1] = force_reg (<BFP:MODE>mode, operands[1]); - real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); - real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); + real_2expN (&cmp, <DSI:bitsize> - 1, <BFP:MODE>mode); + real_2expN (&sub, <DSI:bitsize>, <BFP:MODE>mode); emit_cmp_and_jump_insns (operands[1], const_double_from_real_value (cmp, <BFP:MODE>mode), LT, NULL_RTX, VOIDmode, 0, label1); emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], const_double_from_real_value (sub, <BFP:MODE>mode))); - emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, + emit_insn (gen_fix_trunc<BFP:mode><DSI:mode>2_bfp (operands[0], temp, GEN_INT (BFP_RND_TOWARD_MINF))); emit_jump (label2); emit_label (label1); - emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], + emit_insn (gen_fix_trunc<BFP:mode><DSI:mode>2_bfp (operands[0], operands[1], GEN_INT (BFP_RND_TOWARD_0))); emit_label (label2); @@ -5734,23 +5226,23 @@ ; (dd|td|sf|df|tf)->unsigned (di|si) ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr ; clfdtr, clfxtr, clgdtr, clgxtr -(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" - [(set (match_operand:GPR 0 "register_operand" "=d") - (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) - (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) +(define_insn "*fixuns_trunc<FP:mode><DSI:mode>2_z196" + [(set (match_operand:DSI 0 "register_operand" "=d") + (unsigned_fix:DSI (match_operand:FP 1 "register_operand" "f"))) + (unspec:DSI [(match_operand:DSI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] "TARGET_Z196 && TARGET_HARD_FLOAT - && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" - "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" + && (!TARGET_VX || <DSI:MODE>mode != DImode || <FP:MODE>mode != DFmode)" + "cl<DSI:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" [(set_attr "op_type" "RRF") (set_attr "type" "ftoi")]) -(define_expand "fix_trunc<DSF:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "register_operand" "") - (fix:GPR (match_operand:DSF 1 "register_operand" "")))] +(define_expand "fix_trunc<DSF:mode><DSI:mode>2" + [(set (match_operand:DSI 0 "register_operand" "") + (fix:DSI (match_operand:DSF 1 "register_operand" "")))] "TARGET_HARD_FLOAT" { - emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], + emit_insn (gen_fix_trunc<DSF:mode><DSI:mode>2_bfp (operands[0], operands[1], GEN_INT (BFP_RND_TOWARD_0))); DONE; }) @@ -5770,22 +5262,22 @@ (set_attr "type" "ftoi")]) ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr -(define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" - [(set (match_operand:GPR 0 "register_operand" "=d") - (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) - (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) +(define_insn "*fix_trunc<BFP:mode><DSI:mode>2_bfp" + [(set (match_operand:DSI 0 "register_operand" "=d") + (fix:DSI (match_operand:BFP 1 "register_operand" "f"))) + (unspec:DSI [(match_operand:DSI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT - && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" - "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" + && (!TARGET_VX || <DSI:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" + "c<DSI:gf><BFP:xde>br\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) -(define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" +(define_expand "fix_trunc<BFP:mode><DSI:mode>2_bfp" [(parallel - [(set (match_operand:GPR 0 "register_operand" "=d") - (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) - (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) + [(set (match_operand:DSI 0 "register_operand" "=d") + (fix:DSI (match_operand:BFP 1 "register_operand" "f"))) + (unspec:DSI [(match_operand:DSI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT") ; @@ -5795,7 +5287,7 @@ (define_expand "fix_trunc<mode>di2" [(set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] - "TARGET_ZARCH && TARGET_HARD_DFP" + "TARGET_HARD_DFP" { operands[1] = force_reg (<MODE>mode, operands[1]); emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], @@ -5809,7 +5301,7 @@ (fix:DI (match_operand:DFP 1 "register_operand" "f"))) (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && TARGET_HARD_DFP" + "TARGET_HARD_DFP" "cg<DFP:xde>tr\t%0,%h2,%1" [(set_attr "op_type" "RRF") (set_attr "type" "ftoidfp")]) @@ -5820,9 +5312,9 @@ ; (define_expand "fix_trunctf<mode>2_fpr" - [(parallel [(set (match_operand:GPR 0 "register_operand" "") - (fix:GPR (match_operand:TF 1 "register_operand" ""))) - (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) + [(parallel [(set (match_operand:DSI 0 "register_operand" "") + (fix:DSI (match_operand:TF 1 "register_operand" ""))) + (unspec:DSI [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT && !TARGET_VXE" "") @@ -5836,7 +5328,7 @@ (define_insn "floatdi<mode>2<tf_fpr>" [(set (match_operand:FP 0 "register_operand" "=f,v") (float:FP (match_operand:DI 1 "register_operand" "d,v")))] - "TARGET_ZARCH && TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT" "@ c<xde>g<bt>r\t%0,%1 wcdgb\t%v0,%v1,0,0" @@ -5883,18 +5375,18 @@ ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr -(define_insn "*floatuns<GPR:mode><FP:mode>2" +(define_insn "*floatuns<DSI:mode><FP:mode>2" [(set (match_operand:FP 0 "register_operand" "=f") - (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] + (unsigned_float:FP (match_operand:DSI 1 "register_operand" "d")))] "TARGET_Z196 && TARGET_HARD_FLOAT - && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" - "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" + && (!TARGET_VX || <FP:MODE>mode != DFmode || <DSI:MODE>mode != DImode)" + "c<FP:xde>l<DSI:gf><FP:bt>r\t%0,0,%1,0" [(set_attr "op_type" "RRE") (set_attr "type" "itof<FP:type>")]) -(define_expand "floatuns<GPR:mode><FP:mode>2<tf_fpr>" +(define_expand "floatuns<DSI:mode><FP:mode>2<tf_fpr>" [(set (match_operand:FP 0 "register_operand" "") - (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] + (unsigned_float:FP (match_operand:DSI 1 "register_operand" "")))] "TARGET_Z196 && TARGET_HARD_FLOAT") ; @@ -6257,7 +5749,7 @@ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") (match_operand:TI 2 "general_operand" "") ) ) (clobber (reg:CC CC_REGNUM))])] - "TARGET_ZARCH" + "" { /* For z13 we have vaq which doesn't set CC. */ if (TARGET_VX) @@ -6275,7 +5767,7 @@ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "#" "&& reload_completed" [(parallel @@ -6315,7 +5807,7 @@ (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "@ agfr\t%0,%2 agf\t%0,%2" @@ -6329,7 +5821,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] - "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCLmode)" "@ algfr\t%0,%2 algf\t%0,%2" @@ -6342,7 +5834,7 @@ (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCLmode)" "@ algfr\t%0,%2 algf\t%0,%2" @@ -6354,38 +5846,13 @@ (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "@ algfr\t%0,%2 algf\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) -(define_insn_and_split "*adddi3_31z" - [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") - (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") - (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "#" - "&& reload_completed" - [(parallel - [(set (reg:CCL1 CC_REGNUM) - (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) - (match_dup 7))) - (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) - (parallel - [(set (match_dup 3) (plus:SI - (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) - (match_dup 4)) (match_dup 5))) - (clobber (reg:CC CC_REGNUM))])] - "operands[3] = operand_subword (operands[0], 0, 0, DImode); - operands[4] = operand_subword (operands[1], 0, 0, DImode); - operands[5] = operand_subword (operands[2], 0, 0, DImode); - operands[6] = operand_subword (operands[0], 1, 0, DImode); - operands[7] = operand_subword (operands[1], 1, 0, DImode); - operands[8] = operand_subword (operands[2], 1, 0, DImode);") - ; ; addsi3 instruction pattern(s). ; @@ -6418,9 +5885,9 @@ ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") - (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") - (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") + (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") + (match_operand:DSI 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -6441,11 +5908,11 @@ ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik (define_insn "add<mode>3_carry1_cc" [(set (reg:CCL1 CC_REGNUM) - (compare:CCL1 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") - (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) + (compare:CCL1 (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:DSI 2 "general_operand" " d,d,Op,On,K,R,T,C")) (match_dup 1))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") - (plus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") + (plus:DSI (match_dup 1) (match_dup 2)))] "" "@ al<g>r\t%0,%2 @@ -6464,10 +5931,10 @@ ; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_carry1_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 @@ -6481,11 +5948,11 @@ ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add<mode>3_carry2_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") - (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:DSI 2 "general_operand" " d,d,Op,On,K,R,T,C")) (match_dup 2))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") - (plus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") + (plus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 @@ -6504,10 +5971,10 @@ ; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_carry2_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (match_dup 2))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 @@ -6521,11 +5988,11 @@ ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik (define_insn "*add<mode>3_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") - (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") + (match_operand:DSI 2 "general_operand" " d,d,Op,On,K,R,T,C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") - (plus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") + (plus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ al<g>r\t%0,%2 @@ -6544,10 +6011,10 @@ ; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_cconly" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCLmode)" "@ al<g>r\t%0,%2 @@ -6561,9 +6028,9 @@ ; alr, al, aly, algr, alg, alrk, algrk (define_insn "*add<mode>3_cconly2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") - (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (compare (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,0") + (neg:DSI (match_operand:DSI 2 "general_operand" "d,d,R,T")))) + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode(insn, CCLmode)" "@ al<g>r\t%0,%2 @@ -6577,16 +6044,15 @@ ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" [(set (reg CC_REGNUM) - (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") - (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) + (compare (plus:DSI (match_operand:DSI 1 "nonimmediate_operand" " 0, d,0, 0") + (match_operand:DSI 2 "const_int_operand" " K, K,Os,C")) (const_int 0))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") - (plus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "nonimmediate_operand" "=d, d,d, S") + (plus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") - /* Avoid INT32_MIN on 32 bit. */ - && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" + && INTVAL (operands[2]) != -0x7fffffff - 1))" "@ a<g>hi\t%0,%h2 a<g>hik\t%0,%1,%h2 @@ -6617,12 +6083,12 @@ [(parallel [(set (reg:CCO CC_REGNUM) (compare:CCO (plus:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) + (sign_extend:<DBL> (match_operand:DSI 1 "nonimmediate_operand")) (match_dup 4)) - (sign_extend:<DBL> (plus:GPR (match_dup 1) - (match_operand:GPR 2 "general_operand"))))) - (set (match_operand:GPR 0 "nonimmediate_operand") - (plus:GPR (match_dup 1) (match_dup 2)))]) + (sign_extend:<DBL> (plus:DSI (match_dup 1) + (match_operand:DSI 2 "general_operand"))))) + (set (match_operand:DSI 0 "nonimmediate_operand") + (plus:DSI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) (label_ref (match_operand 3)) @@ -6631,24 +6097,24 @@ { if (CONSTANT_P (operands[2]) && !addv_const_operand (operands[2], GET_MODE (operands[2]))) - operands[2] = force_reg (<GPR:MODE>mode, operands[2]); + operands[2] = force_reg (<DSI:MODE>mode, operands[2]); if (GET_MODE (operands[2]) != VOIDmode) operands[4] = gen_rtx_SIGN_EXTEND (<DBL>mode, operands[2]); else /* This is what CSE does when propagating a constant into the pattern. */ - operands[4] = simplify_unary_operation (SIGN_EXTEND, <GPR:DBL>mode, operands[2], <GPR:MODE>mode); + operands[4] = simplify_unary_operation (SIGN_EXTEND, <DSI:DBL>mode, operands[2], <DSI:MODE>mode); }) ; ark, agrk, ar, ahi, ahik, aghik, a, ay, agr, aghi, ag, asi, agsi (define_insn "*addv<mode>3_ccoverflow" [(set (reg CC_REGNUM) (compare (plus:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d,0,0,0")) - (sign_extend:<DBL> (match_operand:GPR 2 "general_operand" " d,d,K,K,R,T,C"))) - (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S") - (plus:GPR (match_dup 1) (match_dup 2)))] + (sign_extend:<DBL> (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0,d,0,0,0")) + (sign_extend:<DBL> (match_operand:DSI 2 "general_operand" " d,d,K,K,R,T,C"))) + (sign_extend:<DBL> (plus:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "nonimmediate_operand" "=d,d,d,d,d,d,S") + (plus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCOmode)" "@ a<g>r\t%0,%2 @@ -6667,11 +6133,11 @@ (define_insn "*addv<mode>3_ccoverflow_const" [(set (reg CC_REGNUM) (compare (plus:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0")) + (sign_extend:<DBL> (match_operand:DSI 1 "nonimmediate_operand" "%0,d,0")) (match_operand:<DBL> 2 "addv_const_operand" "K,K,C")) - (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,S") - (plus:GPR (match_dup 1) (match_dup 2)))] + (sign_extend:<DBL> (plus:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "nonimmediate_operand" "=d,d,S") + (plus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCOmode)" "@ a<g>hi\t%0,%h2 @@ -6747,7 +6213,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "nonmemory_operand" "")))] - "TARGET_64BIT" + "" { if (GET_CODE (operands[2]) == CONST_INT) { @@ -6764,32 +6230,6 @@ } }) -; For 31 bit we have to prevent the generated pattern from matching -; normal ADDs since la only does a 31 bit add. This is supposed to -; match "force_la_31". -(define_expand "addptrsi3" - [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" ""))) - (use (const_int 0))])] - "!TARGET_64BIT" -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - HOST_WIDE_INT c = INTVAL (operands[2]); - - if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") - && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) - { - operands[2] = force_const_mem (SImode, operands[2]); - operands[2] = force_reg (SImode, operands[2]); - } - else if (!DISP_IN_RANGE (INTVAL (operands[2]))) - operands[2] = force_reg (SImode, operands[2]); - } -}) - ;; ;;- Subtract instructions. ;; @@ -6804,7 +6244,7 @@ (minus:TI (match_operand:TI 1 "register_operand" "") (match_operand:TI 2 "general_operand" "") ) ) (clobber (reg:CC CC_REGNUM))])] - "TARGET_ZARCH" + "" { /* For z13 we have vsq which doesn't set CC. */ if (TARGET_VX) @@ -6822,7 +6262,7 @@ (minus:TI (match_operand:TI 1 "register_operand" "0") (match_operand:TI 2 "general_operand" "do") ) ) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "#" "&& reload_completed" [(parallel @@ -6861,7 +6301,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "@ sgfr\t%0,%2 sgf\t%0,%2" @@ -6876,7 +6316,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] - "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCLmode)" "@ slgfr\t%0,%2 slgf\t%0,%2" @@ -6889,7 +6329,7 @@ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] - "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" + "s390_match_ccmode (insn, CCLmode)" "@ slgfr\t%0,%2 slgf\t%0,%2" @@ -6901,37 +6341,13 @@ (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "@ slgfr\t%0,%2 slgf\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) -(define_insn_and_split "*subdi3_31z" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "#" - "&& reload_completed" - [(parallel - [(set (reg:CCL2 CC_REGNUM) - (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) - (match_dup 7))) - (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) - (parallel - [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) - (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) - (clobber (reg:CC CC_REGNUM))])] - "operands[3] = operand_subword (operands[0], 0, 0, DImode); - operands[4] = operand_subword (operands[1], 0, 0, DImode); - operands[5] = operand_subword (operands[2], 0, 0, DImode); - operands[6] = operand_subword (operands[0], 1, 0, DImode); - operands[7] = operand_subword (operands[1], 1, 0, DImode); - operands[8] = operand_subword (operands[2], 1, 0, DImode);") - ; ; subsi3 instruction pattern(s). ; @@ -6964,9 +6380,9 @@ ; sr, s, sy, sgr, sg, srk, sgrk (define_insn "*sub<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) + [(set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (minus:DSI (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T") ) ) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -6981,11 +6397,11 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "sub<mode>3_borrow_cc" [(set (reg:CCL2 CC_REGNUM) - (compare:CCL2 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare:CCL2 (minus:DSI (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (minus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (minus:DSI (match_dup 1) (match_dup 2)))] "" "@ sl<g>r\t%0,%2 @@ -6999,10 +6415,10 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_borrow_cconly" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (minus:DSI (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (match_dup 1))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL2mode)" "@ sl<g>r\t%0,%2 @@ -7016,11 +6432,11 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cc" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (minus:DSI (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (minus:GPR (match_dup 1) (match_dup 2)))] + (set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (minus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ sl<g>r\t%0,%2 @@ -7034,10 +6450,10 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cc2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T"))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (minus:GPR (match_dup 1) (match_dup 2)))] + (compare (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T"))) + (set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (minus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCL3mode)" "@ sl<g>r\t%0,%2 @@ -7051,10 +6467,10 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cconly" [(set (reg CC_REGNUM) - (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T")) + (compare (minus:DSI (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCLmode)" "@ sl<g>r\t%0,%2 @@ -7069,9 +6485,9 @@ ; slr, sl, sly, slgr, slg, slrk, slgrk (define_insn "*sub<mode>3_cconly2" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") - (match_operand:GPR 2 "general_operand" "d,d,R,T"))) - (clobber (match_scratch:GPR 0 "=d,d,d,d"))] + (compare (match_operand:DSI 1 "register_operand" "0,d,0,0") + (match_operand:DSI 2 "general_operand" "d,d,R,T"))) + (clobber (match_scratch:DSI 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL3mode)" "@ sl<g>r\t%0,%2 @@ -7096,11 +6512,11 @@ [(parallel [(set (reg:CCO CC_REGNUM) (compare:CCO (minus:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) - (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) - (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "nonimmediate_operand") - (minus:GPR (match_dup 1) (match_dup 2)))]) + (sign_extend:<DBL> (match_operand:DSI 1 "nonimmediate_operand")) + (sign_extend:<DBL> (match_operand:DSI 2 "nonimmediate_operand"))) + (sign_extend:<DBL> (minus:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "nonimmediate_operand") + (minus:DSI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) (label_ref (match_operand 3)) @@ -7111,11 +6527,11 @@ (define_insn "*subv<mode>3_ccoverflow" [(set (reg CC_REGNUM) (compare (minus:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "0,d,0,0")) - (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" "d,d,R,T"))) - (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") - (minus:GPR (match_dup 1) (match_dup 2)))] + (sign_extend:<DBL> (match_operand:DSI 1 "nonimmediate_operand" "0,d,0,0")) + (sign_extend:<DBL> (match_operand:DSI 2 "nonimmediate_operand" "d,d,R,T"))) + (sign_extend:<DBL> (minus:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "register_operand" "=d,d,d,d") + (minus:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCOmode)" "@ s<g>r\t%0,%2 @@ -7193,11 +6609,11 @@ ; (define_expand "uaddc<mode>5" - [(match_operand:GPR 0 "register_operand") - (match_operand:GPR 1 "nonimmediate_operand") - (match_operand:GPR 2 "nonimmediate_operand") - (match_operand:GPR 3 "nonimmediate_operand") - (match_operand:GPR 4 "general_operand")] + [(match_operand:DSI 0 "register_operand") + (match_operand:DSI 1 "nonimmediate_operand") + (match_operand:DSI 2 "nonimmediate_operand") + (match_operand:DSI 3 "nonimmediate_operand") + (match_operand:DSI 4 "general_operand")] "TARGET_Z196" { if (operands[4] == const0_rtx) @@ -7222,12 +6638,12 @@ (define_insn "add<mode>3_alc_carry1_cc" [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T")) + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T")) (match_dup 1))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] + (set (match_operand:DSI 0 "register_operand" "=d,d") + (plus:DSI (plus:DSI (match_dup 3) (match_dup 1)) (match_dup 2)))] "" "@ alc<g>r\t%0,%2 @@ -7239,11 +6655,11 @@ (define_insn "*add<mode>3_alc_carry1_cconly" [(set (reg CC_REGNUM) (compare - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T")) + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T")) (match_dup 1))) - (clobber (match_scratch:GPR 0 "=d,d"))] + (clobber (match_scratch:DSI 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ alc<g>r\t%0,%2 @@ -7257,12 +6673,12 @@ (define_insn "*add<mode>3_alc_carry2_cc" [(set (reg CC_REGNUM) (compare - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T")) + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T")) (match_dup 2))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] + (set (match_operand:DSI 0 "register_operand" "=d,d") + (plus:DSI (plus:DSI (match_dup 3) (match_dup 1)) (match_dup 2)))] "s390_match_ccmode (insn, CCL1mode)" "@ alc<g>r\t%0,%2 @@ -7273,11 +6689,11 @@ (define_insn "*add<mode>3_alc_carry2_cconly" [(set (reg CC_REGNUM) (compare - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T")) + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T")) (match_dup 2))) - (clobber (match_scratch:GPR 0 "=d,d"))] + (clobber (match_scratch:DSI 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ alc<g>r\t%0,%2 @@ -7288,12 +6704,12 @@ (define_insn "*add<mode>3_alc_cc" [(set (reg CC_REGNUM) (compare - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T")) + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] + (set (match_operand:DSI 0 "register_operand" "=d,d") + (plus:DSI (plus:DSI (match_dup 3) (match_dup 1)) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ alc<g>r\t%0,%2 @@ -7302,10 +6718,10 @@ ; alcr, alc, alcgr, alcg (define_insn "*add<mode>3_alc" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") - (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,T"))) + [(set (match_operand:DSI 0 "register_operand" "=d,d") + (plus:DSI (plus:DSI (match_operand:DSI 3 "s390_alc_comparison" "") + (match_operand:DSI 1 "nonimmediate_operand" "%0,0")) + (match_operand:DSI 2 "general_operand" "d,T"))) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -7314,11 +6730,11 @@ [(set_attr "op_type" "RRE,RXY")]) (define_expand "usubc<mode>5" - [(match_operand:GPR 0 "register_operand") - (match_operand:GPR 1 "nonimmediate_operand") - (match_operand:GPR 2 "nonimmediate_operand") - (match_operand:GPR 3 "nonimmediate_operand") - (match_operand:GPR 4 "general_operand")] + [(match_operand:DSI 0 "register_operand") + (match_operand:DSI 1 "nonimmediate_operand") + (match_operand:DSI 2 "nonimmediate_operand") + (match_operand:DSI 3 "nonimmediate_operand") + (match_operand:DSI 4 "general_operand")] "TARGET_Z196" { if (operands[4] == const0_rtx) @@ -7342,12 +6758,12 @@ (define_insn "*sub<mode>3_slb_cc" [(set (reg CC_REGNUM) (compare - (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,T")) - (match_operand:GPR 3 "s390_slb_comparison" "")) + (minus:DSI (minus:DSI (match_operand:DSI 1 "nonimmediate_operand" "0,0") + (match_operand:DSI 2 "general_operand" "d,T")) + (match_operand:DSI 3 "s390_slb_comparison" "")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] + (set (match_operand:DSI 0 "register_operand" "=d,d") + (minus:DSI (minus:DSI (match_dup 1) (match_dup 2)) (match_dup 3)))] "s390_match_ccmode (insn, CCLmode)" "@ slb<g>r\t%0,%2 @@ -7357,10 +6773,10 @@ ; slbr, slb, slbgr, slbg (define_insn "*sub<mode>3_slb" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,T")) - (match_operand:GPR 3 "s390_slb_comparison" ""))) + [(set (match_operand:DSI 0 "register_operand" "=d,d") + (minus:DSI (minus:DSI (match_operand:DSI 1 "nonimmediate_operand" "0,0") + (match_operand:DSI 2 "general_operand" "d,T")) + (match_operand:DSI 3 "s390_slb_comparison" ""))) (clobber (reg:CC CC_REGNUM))] "" "@ @@ -7373,12 +6789,12 @@ (define_insn "sub<mode>3_slb_borrow1_cc" [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 - (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,T")) - (match_operand:GPR 3 "s390_slb_comparison" "")) + (minus:DSI (minus:DSI (match_operand:DSI 1 "nonimmediate_operand" "0,0") + (match_operand:DSI 2 "general_operand" "d,T")) + (match_operand:DSI 3 "s390_slb_comparison" "")) (match_dup 1))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] + (set (match_operand:DSI 0 "register_operand" "=d,d") + (minus:DSI (minus:DSI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "@ slb<g>r\t%0,%2 @@ -7387,10 +6803,10 @@ (set_attr "z10prop" "z10_c,*")]) (define_expand "add<mode>cc" - [(match_operand:GPR 0 "register_operand" "") + [(match_operand:DSI 0 "register_operand" "") (match_operand 1 "comparison_operator" "") - (match_operand:GPR 2 "register_operand" "") - (match_operand:GPR 3 "const_int_operand" "")] + (match_operand:DSI 2 "register_operand" "") + (match_operand:DSI 3 "const_int_operand" "")] "" "if (!s390_expand_addcc (GET_CODE (operands[1]), XEXP (operands[1], 0), XEXP (operands[1], 1), @@ -7402,33 +6818,33 @@ ; (define_insn_and_split "*scond<mode>" - [(set (match_operand:GPR 0 "register_operand" "=&d") - (match_operand:GPR 1 "s390_alc_comparison" "")) + [(set (match_operand:DSI 0 "register_operand" "=&d") + (match_operand:DSI 1 "s390_alc_comparison" "")) (clobber (reg:CC CC_REGNUM))] "" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel - [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) + [(set (match_dup 0) (plus:DSI (plus:DSI (match_dup 1) (match_dup 0)) (match_dup 0))) (clobber (reg:CC CC_REGNUM))])] "") (define_insn_and_split "*scond<mode>_neg" - [(set (match_operand:GPR 0 "register_operand" "=&d") - (match_operand:GPR 1 "s390_slb_comparison" "")) + [(set (match_operand:DSI 0 "register_operand" "=&d") + (match_operand:DSI 1 "s390_slb_comparison" "")) (clobber (reg:CC CC_REGNUM))] "" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel - [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) + [(set (match_dup 0) (minus:DSI (minus:DSI (match_dup 0) (match_dup 0)) (match_dup 1))) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (neg:GPR (match_dup 0))) + [(set (match_dup 0) (neg:DSI (match_dup 0))) (clobber (reg:CC CC_REGNUM))])] "") @@ -7436,8 +6852,8 @@ (define_expand "cstore<mode>4" [(set (match_operand:SI 0 "register_operand" "") (match_operator:SI 1 "s390_scond_operator" - [(match_operand:GPR 2 "register_operand" "") - (match_operand:GPR 3 "general_operand" "")]))] + [(match_operand:DSI 2 "register_operand" "") + (match_operand:DSI 3 "general_operand" "")]))] "" "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") @@ -7486,8 +6902,8 @@ ; Such patterns get directly emitted by noce_emit_store_flag. (define_insn_and_split "*cstorecc<mode>_z13" - [(set (match_operand:GPR 0 "register_operand" "=&d") - (match_operator:GPR 1 "s390_comparison" + [(set (match_operand:DSI 0 "register_operand" "=&d") + (match_operator:DSI 1 "s390_comparison" [(match_operand 2 "cc_reg_operand" "c") (match_operand 3 "const_int_operand" "")]))] "TARGET_Z13" @@ -7495,7 +6911,7 @@ "reload_completed" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) - (if_then_else:GPR + (if_then_else:DSI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) (const_int 1) (match_dup 0)))]) @@ -7505,10 +6921,10 @@ ;; (define_expand "mov<mode>cc" - [(set (match_operand:GPR 0 "nonimmediate_operand" "") - (if_then_else:GPR (match_operand 1 "comparison_operator" "") - (match_operand:GPR 2 "loc_operand" "") - (match_operand:GPR 3 "loc_operand" "")))] + [(set (match_operand:DSI 0 "nonimmediate_operand" "") + (if_then_else:DSI (match_operand 1 "comparison_operator" "") + (match_operand:DSI 2 "loc_operand" "") + (match_operand:DSI 3 "loc_operand" "")))] "TARGET_Z196" { if (!TARGET_Z13 && CONSTANT_P (operands[2])) @@ -7566,13 +6982,13 @@ ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr (define_insn "*mov<mode>cc" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") - (if_then_else:GPR + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") + (if_then_else:DSI (match_operator 1 "s390_comparison" [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") (match_operand 5 "const_int_operand" "")]) - (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0") - (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] + (match_operand:DSI 3 "loc_operand" " d,0,d,S,0,K,0,d,0") + (match_operand:DSI 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] "TARGET_Z196" "@ loc<g>r%C1\t%0,%3 @@ -7601,13 +7017,13 @@ (mult:DI (match_operand:DI 1 "nonimmediate_operand") (match_operand:DI 2 "general_operand"))) (clobber (reg:CC CC_REGNUM))])] - "TARGET_ZARCH") + "") (define_insn "*muldi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) (match_operand:DI 1 "register_operand" "0,0")))] - "TARGET_ZARCH" + "" "@ msgfr\t%0,%2 msgf\t%0,%2" @@ -7619,7 +7035,7 @@ (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] - "TARGET_ZARCH" + "" "@ msgr\t%0,%2 msgrkc\t%0,%1,%2 @@ -7709,31 +7125,16 @@ ; mulsidi3 instruction pattern(s). ; -(define_insn "mulsidi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%0,0,0")) - (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] - "!TARGET_ZARCH" - "@ - mr\t%0,%2 - m\t%0,%2 - mfy\t%0,%2" - [(set_attr "op_type" "RR,RX,RXY") - (set_attr "type" "imulsi") - (set_attr "cpu_facility" "*,*,z10")]) - ; Jump to label OP3 if OP1 * OP2 results in a signed overflow (define_expand "mulv<mode>4" [(parallel [(set (reg:CCO CC_REGNUM) (compare:CCO (mult:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "register_operand")) - (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) - (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "register_operand") - (mult:GPR (match_dup 1) (match_dup 2)))]) + (sign_extend:<DBL> (match_operand:DSI 1 "register_operand")) + (sign_extend:<DBL> (match_operand:DSI 2 "nonimmediate_operand"))) + (sign_extend:<DBL> (mult:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "register_operand") + (mult:DSI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) (label_ref (match_operand 3)) @@ -7744,11 +7145,11 @@ (define_insn "*mulv<mode>3_ccoverflow" [(set (reg CC_REGNUM) (compare (mult:<DBL> - (sign_extend:<DBL> (match_operand:GPR 1 "register_operand" "%d,0")) - (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" " d,T"))) - (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (mult:GPR (match_dup 1) (match_dup 2)))] + (sign_extend:<DBL> (match_operand:DSI 1 "register_operand" "%d,0")) + (sign_extend:<DBL> (match_operand:DSI 2 "nonimmediate_operand" " d,T"))) + (sign_extend:<DBL> (mult:DSI (match_dup 1) (match_dup 2))))) + (set (match_operand:DSI 0 "register_operand" "=d,d") + (mult:DSI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCOmode) && TARGET_Z14" "@ ms<g>rkc\t%0,%1,%2 @@ -7761,18 +7162,18 @@ ; ; mlr, ml, mlgr, mlg -(define_insn "umul<dwh><mode>3" - [(set (match_operand:DW 0 "register_operand" "=d,d") - (mult:DW (zero_extend:DW - (match_operand:<DWH> 1 "register_operand" "%0,0")) - (zero_extend:DW - (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] +(define_insn "umulditi3" + [(set (match_operand:TI 0 "register_operand" "=d,d") + (mult:TI (zero_extend:TI + (match_operand:DI 1 "register_operand" "%0,0")) + (zero_extend:TI + (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] "" "@ - ml<tg>r\t%0,%2 - ml<tg>\t%0,%2" + mlgr\t%0,%2 + mlg\t%0,%2" [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "imul<dwh>")]) + (set_attr "type" "imuldi")]) ; ; mul(tf|df|sf|td|dd)3 instruction pattern(s). @@ -7844,7 +7245,7 @@ (set (match_operand:DI 3 "general_operand" "") (mod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "TARGET_ZARCH" + "" { rtx div_equal, mod_equal; rtx_insn *insn; @@ -7873,7 +7274,7 @@ (match_operand:DI 2 "general_operand" "d,T"))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] - "TARGET_ZARCH" + "" "@ dsgr\t%0,%2 dsg\t%0,%2" @@ -7889,193 +7290,73 @@ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,T")))) (const_int 64)) - (zero_extend:TI - (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] - "TARGET_ZARCH" - "@ - dsgfr\t%0,%2 - dsgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "idiv")]) - -; -; udivmoddi4 instruction pattern(s). -; - -(define_expand "udivmoddi4" - [(parallel [(set (match_operand:DI 0 "general_operand" "") - (udiv:DI (match_operand:DI 1 "general_operand" "") - (match_operand:DI 2 "nonimmediate_operand" ""))) - (set (match_operand:DI 3 "general_operand" "") - (umod:DI (match_dup 1) (match_dup 2)))]) - (clobber (match_dup 4))] - "TARGET_ZARCH" -{ - rtx div_equal, mod_equal, equal; - rtx_insn *insn; - - div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); - mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); - equal = gen_rtx_IOR (TImode, - gen_rtx_ASHIFT (TImode, - gen_rtx_ZERO_EXTEND (TImode, mod_equal), - GEN_INT (64)), - gen_rtx_ZERO_EXTEND (TImode, div_equal)); - - operands[4] = gen_reg_rtx(TImode); - emit_clobber (operands[4]); - emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); - emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); - - insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); - set_unique_reg_note (insn, REG_EQUAL, equal); - - insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); - set_unique_reg_note (insn, REG_EQUAL, div_equal); - - insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); - set_unique_reg_note (insn, REG_EQUAL, mod_equal); - - DONE; -}) - -(define_insn "udivmodtidi3" - [(set (match_operand:TI 0 "register_operand" "=d,d") - (ior:TI - (ashift:TI - (zero_extend:TI - (truncate:DI - (umod:TI (match_operand:TI 1 "register_operand" "0,0") - (zero_extend:TI - (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) - (const_int 64)) - (zero_extend:TI - (truncate:DI - (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] - "TARGET_ZARCH" - "@ - dlgr\t%0,%2 - dlg\t%0,%2" - [(set_attr "op_type" "RRE,RXY") - (set_attr "type" "idiv")]) - -; -; divmodsi4 instruction pattern(s). -; - -(define_expand "divmodsi4" - [(parallel [(set (match_operand:SI 0 "general_operand" "") - (div:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "nonimmediate_operand" ""))) - (set (match_operand:SI 3 "general_operand" "") - (mod:SI (match_dup 1) (match_dup 2)))]) - (clobber (match_dup 4))] - "!TARGET_ZARCH" -{ - rtx div_equal, mod_equal, equal; - rtx_insn *insn; - - div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); - mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); - equal = gen_rtx_IOR (DImode, - gen_rtx_ASHIFT (DImode, - gen_rtx_ZERO_EXTEND (DImode, mod_equal), - GEN_INT (32)), - gen_rtx_ZERO_EXTEND (DImode, div_equal)); - - operands[4] = gen_reg_rtx(DImode); - emit_insn (gen_extendsidi2 (operands[4], operands[1])); - - insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); - set_unique_reg_note (insn, REG_EQUAL, equal); - - insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); - set_unique_reg_note (insn, REG_EQUAL, div_equal); - - insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); - set_unique_reg_note (insn, REG_EQUAL, mod_equal); - - DONE; -}) - -(define_insn "divmoddisi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ior:DI - (ashift:DI - (zero_extend:DI - (truncate:SI - (mod:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) - (const_int 32)) - (zero_extend:DI - (truncate:SI - (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] - "!TARGET_ZARCH" - "@ - dr\t%0,%2 - d\t%0,%2" - [(set_attr "op_type" "RR,RX") + (zero_extend:TI + (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] + "" + "@ + dsgfr\t%0,%2 + dsgf\t%0,%2" + [(set_attr "op_type" "RRE,RXY") (set_attr "type" "idiv")]) ; -; udivsi3 and umodsi3 instruction pattern(s). +; udivmoddi4 instruction pattern(s). ; -(define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "general_operand" "") - (udiv:SI (match_operand:SI 1 "general_operand" "") - (match_operand:SI 2 "nonimmediate_operand" ""))) - (set (match_operand:SI 3 "general_operand" "") - (umod:SI (match_dup 1) (match_dup 2)))]) +(define_expand "udivmoddi4" + [(parallel [(set (match_operand:DI 0 "general_operand" "") + (udiv:DI (match_operand:DI 1 "general_operand" "") + (match_operand:DI 2 "nonimmediate_operand" ""))) + (set (match_operand:DI 3 "general_operand" "") + (umod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] - "!TARGET_ZARCH" + "" { rtx div_equal, mod_equal, equal; rtx_insn *insn; - div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); - mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); - equal = gen_rtx_IOR (DImode, - gen_rtx_ASHIFT (DImode, - gen_rtx_ZERO_EXTEND (DImode, mod_equal), - GEN_INT (32)), - gen_rtx_ZERO_EXTEND (DImode, div_equal)); + div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); + mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); + equal = gen_rtx_IOR (TImode, + gen_rtx_ASHIFT (TImode, + gen_rtx_ZERO_EXTEND (TImode, mod_equal), + GEN_INT (64)), + gen_rtx_ZERO_EXTEND (TImode, div_equal)); - operands[4] = gen_reg_rtx(DImode); + operands[4] = gen_reg_rtx(TImode); emit_clobber (operands[4]); - emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); - emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); + emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); + emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); - insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); + insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); set_unique_reg_note (insn, REG_EQUAL, equal); - insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); + insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); set_unique_reg_note (insn, REG_EQUAL, div_equal); - insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); + insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); set_unique_reg_note (insn, REG_EQUAL, mod_equal); DONE; }) -(define_insn "udivmoddisi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ior:DI - (ashift:DI - (zero_extend:DI - (truncate:SI - (umod:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) - (const_int 32)) - (zero_extend:DI - (truncate:SI - (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] - "!TARGET_ZARCH" - "@ - dlr\t%0,%2 - dl\t%0,%2" +(define_insn "udivmodtidi3" + [(set (match_operand:TI 0 "register_operand" "=d,d") + (ior:TI + (ashift:TI + (zero_extend:TI + (truncate:DI + (umod:TI (match_operand:TI 1 "register_operand" "0,0") + (zero_extend:TI + (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) + (const_int 64)) + (zero_extend:TI + (truncate:DI + (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] + "" + "@ + dlgr\t%0,%2 + dlg\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "type" "idiv")]) @@ -8125,7 +7406,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d,d, d") (and:DI (match_dup 1) (match_dup 2)))] - "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" + "s390_match_ccmode(insn, CCTmode)" "@ ngr\t%0,%2 ngrk\t%0,%1,%2 @@ -8142,8 +7423,7 @@ (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d,d, d"))] - "TARGET_ZARCH - && s390_match_ccmode(insn, CCTmode) + "s390_match_ccmode(insn, CCTmode) /* Do not steal TM patterns. */ && s390_single_part (operands[2], DImode, HImode, 0) < 0" "@ @@ -8164,7 +7444,7 @@ (match_operand:DI 2 "general_operand" "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ # # @@ -8209,11 +7489,11 @@ ;; These two are what combine generates for (ashift (zero_extract)). (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (and:GPR (lshiftrt:GPR - (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] + [(set (match_operand:DSI 0 "register_operand" "=d") + (and:DSI (lshiftrt:DSI + (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "contiguous_bitmask_nowrap_operand" "")))] "<z10_or_zEC12_cond> /* Note that even for the SImode pattern, the rotate is always DImode. */ && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), @@ -8239,11 +7519,11 @@ (set_attr "mnemonic" "<risbg_n>")]) (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (and:GPR (ashift:GPR - (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "nonzero_shift_count_operand" "")) - (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] + [(set (match_operand:DSI 0 "register_operand" "=d") + (and:DSI (ashift:DSI + (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "nonzero_shift_count_operand" "")) + (match_operand:DSI 3 "contiguous_bitmask_nowrap_operand" "")))] "<z10_or_zEC12_cond> && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), INTVAL (operands[3])) @@ -8312,7 +7592,7 @@ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, z10_super_E1,z10_super_E1,z10_super_E1")]) -(define_insn "*andsi3_zarch" +(define_insn "*andsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, d, d, d,d,d,d,d, d, AQ,Q") (and:SI (match_operand:SI 1 "nonimmediate_operand" @@ -8320,7 +7600,7 @@ (match_operand:SI 2 "general_operand" " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ # # @@ -8349,21 +7629,6 @@ *, *")]) -(define_insn "*andsi3_esa" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") - (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - nr\t%0,%2 - n\t%0,%2 - # - #" - [(set_attr "op_type" "RR,RX,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) - - (define_split [(set (match_operand:SI 0 "s_operand" "") (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) @@ -8378,12 +7643,12 @@ ; andhi3 instruction pattern(s). ; -(define_insn "*andhi3_zarch" +(define_insn "*andhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 nrk\t%0,%1,%2 @@ -8395,20 +7660,6 @@ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") ]) -(define_insn "*andhi3_esa" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - nr\t%0,%2 - # - #" - [(set_attr "op_type" "RR,SI,SS") - (set_attr "z10prop" "z10_super_E1,*,*") -]) - (define_split [(set (match_operand:HI 0 "s_operand" "") (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) @@ -8423,12 +7674,12 @@ ; andqi3 instruction pattern(s). ; -(define_insn "*andqi3_zarch" +(define_insn "*andqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 nrk\t%0,%1,%2 @@ -8440,28 +7691,15 @@ (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) -(define_insn "*andqi3_esa" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") - (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - nr\t%0,%2 - ni\t%S0,%b2 - #" - [(set_attr "op_type" "RR,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super,*")]) - ; ; And with complement ; ; c = ~b & a = (b & a) ^ a (define_insn_and_split "*andc_split_<mode>" - [(set (match_operand:GPR 0 "nonimmediate_operand" "") - (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) - (match_operand:GPR 2 "general_operand" ""))) + [(set (match_operand:DSI 0 "nonimmediate_operand" "") + (and:DSI (not:DSI (match_operand:DSI 1 "nonimmediate_operand" "")) + (match_operand:DSI 2 "general_operand" ""))) (clobber (reg:CC CC_REGNUM))] "!TARGET_Z15 && ! reload_completed @@ -8473,10 +7711,10 @@ "&& 1" [ (parallel - [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) + [(set (match_dup 3) (and:DSI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) + [(set (match_dup 0) (xor:DSI (match_dup 3) (match_dup 2))) (clobber (reg:CC CC_REGNUM))])] { if (reg_overlap_mentioned_p (operands[0], operands[2])) @@ -8568,7 +7806,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d,d") (ior:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCTmode)" "@ ogr\t%0,%2 ogrk\t%0,%1,%2 @@ -8583,7 +7821,7 @@ (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d,d"))] - "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCTmode)" "@ ogr\t%0,%2 ogrk\t%0,%1,%2 @@ -8600,7 +7838,7 @@ (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ oihh\t%0,%i2 oihl\t%0,%i2 @@ -8676,12 +7914,12 @@ (set_attr "cpu_facility" "*,*,z196,*,longdisp") (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) -(define_insn "*iorsi3_zarch" +(define_insn "*iorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ oilh\t%0,%i2 oill\t%0,%i2 @@ -8704,20 +7942,6 @@ *, *")]) -(define_insn "*iorsi3_esa" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") - (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - or\t%0,%2 - o\t%0,%2 - # - #" - [(set_attr "op_type" "RR,RX,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) - (define_split [(set (match_operand:SI 0 "s_operand" "") (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) @@ -8732,12 +7956,12 @@ ; iorhi3 instruction pattern(s). ; -(define_insn "*iorhi3_zarch" +(define_insn "*iorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 ork\t%0,%1,%2 @@ -8748,19 +7972,6 @@ (set_attr "cpu_facility" "*,z196,*,*,*") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) -(define_insn "*iorhi3_esa" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") - (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - or\t%0,%2 - # - #" - [(set_attr "op_type" "RR,SI,SS") - (set_attr "z10prop" "z10_super_E1,*,*")]) - (define_split [(set (match_operand:HI 0 "s_operand" "") (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) @@ -8775,12 +7986,12 @@ ; iorqi3 instruction pattern(s). ; -(define_insn "*iorqi3_zarch" +(define_insn "*iorqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 ork\t%0,%1,%2 @@ -8793,57 +8004,44 @@ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, z10_super,z10_super,*")]) -(define_insn "*iorqi3_esa" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") - (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" - "@ - or\t%0,%2 - oi\t%S0,%b2 - #" - [(set_attr "op_type" "RR,SI,SS") - (set_attr "z10prop" "z10_super_E1,z10_super,*")]) - ; ; And/Or with complement ; ; ncrk, ncgrk, ocrk, ocgrk -(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc" +(define_insn "*<ANDOR:bitops_name>c<DSI:mode>_cc" [(set (reg CC_REGNUM) (compare - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (match_operand:GPR 2 "register_operand" "d")) + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (match_operand:DSI 2 "register_operand" "d")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (ANDOR:GPR (not:GPR (match_dup 1)) + (set (match_operand:DSI 0 "register_operand" "=d") + (ANDOR:DSI (not:DSI (match_dup 1)) (match_dup 2)))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" + "<ANDOR:noxa>c<DSI:g>rk\t%0,%2,%1" [(set_attr "op_type" "RRF")]) ; ncrk, ncgrk, ocrk, ocgrk -(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly" +(define_insn "*<ANDOR:bitops_name>c<DSI:mode>_cconly" [(set (reg CC_REGNUM) (compare - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (match_operand:GPR 2 "register_operand" "d")) + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (match_operand:DSI 2 "register_operand" "d")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" + "<ANDOR:noxa>c<DSI:g>rk\t%0,%2,%1" [(set_attr "op_type" "RRF")]) ; ncrk, ncgrk, ocrk, ocgrk -(define_insn "*<ANDOR:bitops_name>c<GPR:mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (match_operand:GPR 2 "register_operand" "d"))) +(define_insn "*<ANDOR:bitops_name>c<DSI:mode>" + [(set (match_operand:DSI 0 "register_operand" "=d") + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (match_operand:DSI 2 "register_operand" "d"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z15" - "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" + "<ANDOR:noxa>c<DSI:g>rk\t%0,%2,%1" [(set_attr "op_type" "RRF")]) ; @@ -8851,48 +8049,48 @@ ; ; nnrk, nngrk, nork, nogrk -(define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc" +(define_insn "*n<ANDOR:inv_bitops_name><DSI:mode>_cc" [(set (reg CC_REGNUM) (compare - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (not:GPR (match_operand:GPR 2 "register_operand" "d"))) + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (not:DSI (match_operand:DSI 2 "register_operand" "d"))) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (ANDOR:GPR (not:GPR (match_dup 1)) - (not:GPR (match_dup 2))))] + (set (match_operand:DSI 0 "register_operand" "=d") + (ANDOR:DSI (not:DSI (match_dup 1)) + (not:DSI (match_dup 2))))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" + "n<ANDOR:inv_no><DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ; nnrk, nngrk, nork, nogrk (define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly" [(set (reg CC_REGNUM) (compare - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (not:GPR (match_operand:GPR 2 "register_operand" "d"))) + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (not:DSI (match_operand:DSI 2 "register_operand" "d"))) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" + "n<ANDOR:inv_no><DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ; nnrk, nngrk, nork, nogrk (define_insn "*n<ANDOR:inv_bitops_name><mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) - (not:GPR (match_operand:GPR 2 "register_operand" "d")))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (ANDOR:DSI (not:DSI (match_operand:DSI 1 "register_operand" "d")) + (not:DSI (match_operand:DSI 2 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z15" - "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" + "n<ANDOR:inv_no><DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ; Use NAND for bit inversion (define_insn "*not<mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (not:GPR (match_operand:GPR 1 "register_operand" "d"))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (not:DSI (match_operand:DSI 1 "register_operand" "d"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z15" - "nn<GPR:g>rk\t%0,%1,%1" + "nn<DSI:g>rk\t%0,%1,%1" [(set_attr "op_type" "RRF")]) ; @@ -8993,7 +8191,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d,d") (xor:DI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCTmode)" "@ xgr\t%0,%2 xgrk\t%0,%1,%2 @@ -9008,7 +8206,7 @@ (match_operand:DI 2 "general_operand" " d,d,T")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d,d"))] - "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" + "s390_match_ccmode(insn, CCTmode)" "@ xgr\t%0,%2 xgrk\t%0,%1,%2 @@ -9022,7 +8220,7 @@ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" + "s390_logical_operator_ok_p (operands)" "@ xihf\t%0,%k2 xilf\t%0,%k2 @@ -9265,39 +8463,39 @@ ; ; nxrk, nxgrk -(define_insn "*nxor<GPR:mode>_cc" +(define_insn "*nxor<DSI:mode>_cc" [(set (reg CC_REGNUM) (compare - (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d"))) + (not:DSI (xor:DSI (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "register_operand" "d"))) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (xor:GPR (not:GPR (match_dup 1)) + (set (match_operand:DSI 0 "register_operand" "=d") + (xor:DSI (not:DSI (match_dup 1)) (match_dup 2)))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "nx<GPR:g>rk\t%0,%1,%2" + "nx<DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ; nxrk, nxgrk (define_insn "*nxor<mode>_cconly" [(set (reg CC_REGNUM) (compare - (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d"))) + (not:DSI (xor:DSI (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "register_operand" "d"))) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" - "nx<GPR:g>rk\t%0,%1,%2" + "nx<DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ; nxrk, nxgrk (define_insn "*nxor<mode>" - [(set (match_operand:GPR 0 "register_operand" "=d") - (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d")))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (not:DSI (xor:DSI (match_operand:DSI 1 "register_operand" "d") + (match_operand:DSI 2 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z15" - "nx<GPR:g>rk\t%0,%1,%2" + "nx<DSI:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) ;; @@ -9324,7 +8522,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_dup 1))))] - "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" + "s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9333,7 +8531,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9341,10 +8539,10 @@ ; lcr, lcgr (define_insn "*neg<mode>2_cc" [(set (reg CC_REGNUM) - (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) + (compare (neg:DSI (match_operand:DSI 1 "register_operand" "d")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (neg:GPR (match_dup 1)))] + (set (match_operand:DSI 0 "register_operand" "=d") + (neg:DSI (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9353,9 +8551,9 @@ ; lcr, lcgr (define_insn "*neg<mode>2_cconly" [(set (reg CC_REGNUM) - (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) + (compare (neg:DSI (match_operand:DSI 1 "register_operand" "d")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9363,91 +8561,14 @@ ; lcr, lcgr (define_insn "*neg<mode>2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) (clobber (reg:CC CC_REGNUM))] "" "lc<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") (set_attr "z10prop" "z10_super_c_E1")]) -(define_insn "*negdi2_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "#") - -; Split a DImode NEG on 31bit into 2 SImode NEGs - -; Doing the twos complement separately on the SImode parts does an -; unwanted +1 on the high part which needs to be subtracted afterwards -; ... unless the +1 on the low part created an overflow. - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (match_operand:DI 1 "register_operand" ""))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH - && reload_completed - && ((REG_P (operands[0]) && REG_P (operands[1]) - && REGNO (operands[0]) == REGNO (operands[1])) - || s390_split_ok_p (operands[0], operands[1], DImode, 0))" - [(parallel - [(set (match_dup 2) (neg:SI (match_dup 3))) - (clobber (reg:CC CC_REGNUM))]) - (parallel - [(set (reg:CCAP CC_REGNUM) - (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) - (set (match_dup 4) (neg:SI (match_dup 5)))]) - (set (pc) - (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) - (pc) - (label_ref (match_dup 6)))) - (parallel - [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) - (clobber (reg:CC CC_REGNUM))]) - (match_dup 6)] - "operands[2] = operand_subword (operands[0], 0, 0, DImode); - operands[3] = operand_subword (operands[1], 0, 0, DImode); - operands[4] = operand_subword (operands[0], 1, 0, DImode); - operands[5] = operand_subword (operands[1], 1, 0, DImode); - operands[6] = gen_label_rtx ();") - -; Like above but first make a copy of the low part of the src operand -; since it might overlap with the high part of the destination. - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (match_operand:DI 1 "register_operand" ""))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH - && s390_split_ok_p (operands[0], operands[1], DImode, 1) - && reload_completed" - [; Make a backup of op5 first - (set (match_dup 4) (match_dup 5)) - ; Setting op2 here might clobber op5 - (parallel - [(set (match_dup 2) (neg:SI (match_dup 3))) - (clobber (reg:CC CC_REGNUM))]) - (parallel - [(set (reg:CCAP CC_REGNUM) - (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) - (set (match_dup 4) (neg:SI (match_dup 4)))]) - (set (pc) - (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) - (pc) - (label_ref (match_dup 6)))) - (parallel - [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) - (clobber (reg:CC CC_REGNUM))]) - (match_dup 6)] - "operands[2] = operand_subword (operands[0], 0, 0, DImode); - operands[3] = operand_subword (operands[1], 0, 0, DImode); - operands[4] = operand_subword (operands[0], 1, 0, DImode); - operands[5] = operand_subword (operands[1], 1, 0, DImode); - operands[6] = gen_label_rtx ();") - ; ; neg(tf|df|sf)2 instruction pattern(s). ; @@ -9525,7 +8646,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_dup 1))))] - "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" + "s390_match_ccmode (insn, CCAmode)" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9534,7 +8655,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9542,10 +8663,10 @@ ; lpr, lpgr (define_insn "*abs<mode>2_cc" [(set (reg CC_REGNUM) - (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) + (compare (abs:DSI (match_operand:DI 1 "register_operand" "d")) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (abs:GPR (match_dup 1)))] + (set (match_operand:DSI 0 "register_operand" "=d") + (abs:DSI (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9554,9 +8675,9 @@ ; lpr, lpgr (define_insn "*abs<mode>2_cconly" [(set (reg CC_REGNUM) - (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) + (compare (abs:DSI (match_operand:DSI 1 "register_operand" "d")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9564,8 +8685,8 @@ ; lpr, lpgr (define_insn "abs<mode>2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (abs:DSI (match_operand:DSI 1 "register_operand" "d"))) (clobber (reg:CC CC_REGNUM))] "" "lp<g>r\t%0,%1" @@ -9646,10 +8767,10 @@ (define_expand "<minmaxname><mode>3" [(set (reg:<minmaxcc> CC_REGNUM) - (compare:<minmaxcc> (match_operand:GPR 1 "loc_operand") - (match_operand:GPR 2 "loc_operand"))) - (set (match_operand:GPR 0 "nonimmediate_operand") - (if_then_else:GPR (MINMAXOP (reg:<minmaxcc> CC_REGNUM) (const_int 0)) + (compare:<minmaxcc> (match_operand:DSI 1 "loc_operand") + (match_operand:DSI 2 "loc_operand"))) + (set (match_operand:DSI 0 "nonimmediate_operand") + (if_then_else:DSI (MINMAXOP (reg:<minmaxcc> CC_REGNUM) (const_int 0)) (match_dup 1) (match_dup 2)))] "TARGET_Z196") @@ -9671,7 +8792,7 @@ (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] - "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" + "s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9681,7 +8802,7 @@ (neg:DI (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" "lngfr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "z10prop" "z10_c")]) @@ -9689,10 +8810,10 @@ ; lnr, lngr (define_insn "*negabs<mode>2_cc" [(set (reg CC_REGNUM) - (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) + (compare (neg:DSI (abs:DSI (match_operand:DSI 1 "register_operand" "d"))) (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d") - (neg:GPR (abs:GPR (match_dup 1))))] + (set (match_operand:DSI 0 "register_operand" "=d") + (neg:DSI (abs:DSI (match_dup 1))))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9701,9 +8822,9 @@ ; lnr, lngr (define_insn "*negabs<mode>2_cconly" [(set (reg CC_REGNUM) - (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) + (compare (neg:DSI (abs:DSI (match_operand:DSI 1 "register_operand" "d"))) (const_int 0))) - (clobber (match_scratch:GPR 0 "=d"))] + (clobber (match_scratch:DSI 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" [(set_attr "op_type" "RR<E>") @@ -9711,8 +8832,8 @@ ; lnr, lngr (define_insn "*negabs<mode>2" - [(set (match_operand:GPR 0 "register_operand" "=d") - (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) + [(set (match_operand:DSI 0 "register_operand" "=d") + (neg:DSI (abs:DSI (match_operand:DSI 1 "register_operand" "d")))) (clobber (reg:CC CC_REGNUM))] "" "ln<g>r\t%0,%1" @@ -9818,9 +8939,9 @@ (define_expand "clzdi2" [(set (match_operand:DI 0 "register_operand" "=d") (clz:DI (match_operand:DI 1 "register_operand" "d")))] - "TARGET_EXTIMM && TARGET_ZARCH" + "TARGET_EXTIMM" { - if (!(TARGET_Z17 && TARGET_64BIT)) + if (!TARGET_Z17) { rtx_insn *insn; rtx clz_equal; @@ -9841,7 +8962,7 @@ (define_insn "*clzg" [(set (match_operand:DI 0 "register_operand" "=d") (clz:DI (match_operand:DI 1 "register_operand" "d")))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "clzg\t%0,%1" [(set_attr "op_type" "RRE")]) @@ -9858,14 +8979,14 @@ (subreg:SI (clz:DI (match_dup 1)) 4)))))) (clobber (reg:CC CC_REGNUM))] "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 - && TARGET_EXTIMM && TARGET_ZARCH" + && TARGET_EXTIMM" "flogr\t%0,%1" [(set_attr "op_type" "RRE")]) (define_expand "clzsi2" [(match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "register_operand" "")] - "TARGET_EXTIMM && TARGET_ZARCH" + "TARGET_EXTIMM" { rtx extreg = gen_reg_rtx (DImode); rtx clzreg = gen_reg_rtx (DImode); @@ -9883,7 +9004,7 @@ (define_insn "ctzdi2" [(set (match_operand:DI 0 "register_operand" "=d") (ctz:DI (match_operand:DI 1 "register_operand" "d")))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" "ctzg\t%0,%1" [(set_attr "op_type" "RRE")]) @@ -9892,7 +9013,7 @@ (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) (set (match_dup 3) (ctz:DI (match_dup 2))) (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 4))] - "TARGET_Z17 && TARGET_64BIT" + "TARGET_Z17" { operands[2] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode); @@ -9907,16 +9028,16 @@ ; (define_expand "rotl<mode>3" - [(set (match_operand:GPR 0 "register_operand" "") - (rotate:GPR (match_operand:GPR 1 "register_operand" "") + [(set (match_operand:DSI 0 "register_operand" "") + (rotate:DSI (match_operand:DSI 1 "register_operand" "") (match_operand:QI 2 "shift_count_operand" "")))] "" "") ; rll, rllg (define_insn "*rotl<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") + [(set (match_operand:DSI 0 "register_operand" "=d") + (rotate:DSI (match_operand:DSI 1 "register_operand" "d") (match_operand:QI 2 "shift_count_operand" "jsc")))] "" "rll<g>\t%0,%1,%Y2" @@ -9940,24 +9061,12 @@ "" "") -; ESA 64 bit register pair shift with reg or imm shift count -; sldl, srdl -(define_insn "*<shift>di3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:QI 2 "shift_count_operand" "jsc")))] - "!TARGET_ZARCH" - "s<lr>dl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg") - (set_attr "z196prop" "z196_cracked")]) - ; 64 bit register shift with reg or imm shift count ; sll, srl, sllg, srlg, sllk, srlk (define_insn "*<shift><mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d, d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") + [(set (match_operand:DSI 0 "register_operand" "=d, d") + (SHIFT:DSI (match_operand:DSI 1 "register_operand" "<d0>, d") (match_operand:QI 2 "shift_count_operand" "jsc,jsc")))] "" "@ @@ -9982,21 +9091,11 @@ "" "") -(define_insn "*ashrdi3_31<setcc><cconly>" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:QI 2 "shift_count_operand" "jsc"))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - ; sra, srag (define_insn "*ashr<mode>3<setcc><cconly>" - [(set (match_operand:GPR 0 "register_operand" "=d, d") - (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") + [(set (match_operand:DSI 0 "register_operand" "=d, d") + (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "<d0>, d") (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) (clobber (reg:CC CC_REGNUM))] "" @@ -10016,8 +9115,8 @@ (define_expand "cbranch<mode>4" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" - [(match_operand:GPR 1 "register_operand" "") - (match_operand:GPR 2 "general_operand" "")]) + [(match_operand:DSI 1 "register_operand" "") + (match_operand:DSI 2 "general_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] "" @@ -10184,8 +9283,8 @@ (define_expand "ctrap<mode>4" [(trap_if (match_operator 0 "comparison_operator" - [(match_operand:GPR 1 "register_operand" "") - (match_operand:GPR 2 "general_operand" "")]) + [(match_operand:DSI 1 "register_operand" "") + (match_operand:DSI 2 "general_operand" "")]) (match_operand 3 "const0_operand" ""))] "" { @@ -10221,8 +9320,8 @@ ; crt, cgrt, cit, cgit (define_insn "*cmp_and_trap_signed_int<mode>" [(trap_if (match_operator 0 "s390_signed_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "nonmemory_operand" "d,K")]) + [(match_operand:DSI 1 "register_operand" "d,d") + (match_operand:DSI 2 "nonmemory_operand" "d,K")]) (const_int 0))] "TARGET_Z10" "@ @@ -10235,8 +9334,8 @@ ; clrt, clgrt, clfit, clgit, clt, clgt (define_insn "*cmp_and_trap_unsigned_int<mode>" [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" - [(match_operand:GPR 1 "register_operand" "d,d,d") - (match_operand:GPR 2 "general_operand" "d,D,S")]) + [(match_operand:DSI 1 "register_operand" "d,d,d") + (match_operand:DSI 2 "general_operand" "d,D,S")]) (const_int 0))] "TARGET_Z10" "@ @@ -10250,10 +9349,10 @@ ; lat, lgat (define_insn "*load_and_trap<mode>" - [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") + [(trap_if (eq (match_operand:DSI 0 "memory_operand" "T") (const_int 0)) (const_int 0)) - (set (match_operand:GPR 1 "register_operand" "=d") + (set (match_operand:DSI 1 "register_operand" "=d") (match_dup 0))] "TARGET_ZEC12" "l<g>at\t%1,%0" @@ -10272,19 +9371,19 @@ ; necessary to load the compare and the increment values into a ; register pair as needed by brxle. -(define_insn_and_split "*brx_stage1_<GPR:mode>" +(define_insn_and_split "*brx_stage1_<DSI:mode>" [(set (pc) (if_then_else (match_operator 6 "s390_brx_operator" - [(plus:GPR (match_operand:GPR 1 "register_operand" "") - (match_operand:GPR 2 "general_operand" "")) - (match_operand:GPR 3 "register_operand" "")]) + [(plus:DSI (match_operand:DSI 1 "register_operand" "") + (match_operand:DSI 2 "general_operand" "")) + (match_operand:DSI 3 "register_operand" "")]) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:GPR 4 "nonimmediate_operand" "") - (plus:GPR (match_dup 1) (match_dup 2))) + (set (match_operand:DSI 4 "nonimmediate_operand" "") + (plus:DSI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REGNUM)) - (clobber (match_scratch:GPR 5 ""))] + (clobber (match_scratch:DSI 5 ""))] "" "#" "!reload_completed && !reload_in_progress" @@ -10293,20 +9392,20 @@ (parallel [(set (pc) (if_then_else (match_op_dup 6 - [(plus:GPR (match_dup 1) (match_dup 7)) + [(plus:DSI (match_dup 1) (match_dup 7)) (match_dup 8)]) (label_ref (match_dup 0)) (pc))) (set (match_dup 4) - (plus:GPR (match_dup 1) (match_dup 7))) + (plus:DSI (match_dup 1) (match_dup 7))) (clobber (match_dup 5)) (clobber (reg:CC CC_REGNUM))])] { - rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); - operands[7] = gen_lowpart (<GPR:MODE>mode, - gen_highpart (word_mode, dreg)); - operands[8] = gen_lowpart (<GPR:MODE>mode, - gen_lowpart (word_mode, dreg)); + rtx dreg = gen_reg_rtx (TImode); + operands[7] = gen_lowpart (<DSI:MODE>mode, + gen_highpart (DImode, dreg)); + operands[8] = gen_lowpart (<DSI:MODE>mode, + gen_lowpart (DImode, dreg)); }) ; brxlg, brxhg @@ -10325,7 +9424,7 @@ (subreg:DI (match_dup 2) 0))) (clobber (match_scratch:DI 4 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" { if (which_alternative != 0) return "#"; @@ -10368,7 +9467,7 @@ (subreg:SI (match_dup 2) 4))) (clobber (match_scratch:SI 4 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" { if (which_alternative != 0) return "#"; @@ -10395,49 +9494,6 @@ (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 6) (const_int 14)))]) -; brxle, brxh - -(define_insn_and_split "*brx_31bit" - [(set (pc) - (if_then_else - (match_operator 5 "s390_brx_operator" - [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") - (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) - (subreg:SI (match_dup 2) 4)]) - (label_ref (match_operand 0 "" "")) - (pc))) - (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") - (plus:SI (match_dup 1) - (subreg:SI (match_dup 2) 0))) - (clobber (match_scratch:SI 4 "=X,&1,&?d")) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH" -{ - if (which_alternative != 0) - return "#"; - else if (get_attr_length (insn) == 6) - return "brx%C5\t%1,%2,%l0"; - else - return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; -} - "&& reload_completed - && (!REG_P (operands[3]) - || !rtx_equal_p (operands[1], operands[3]))" - [(set (match_dup 4) (match_dup 1)) - (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) - (clobber (reg:CC CC_REGNUM))]) - (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) - (set (match_dup 3) (match_dup 4)) - (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) - (label_ref (match_dup 0)) - (pc)))] - "" - [(set_attr "op_type" "RSI") - (set_attr "type" "branch") - (set (attr "length") - (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) - (const_int 6) (const_int 14)))]) - ;; branch on count @@ -10448,7 +9504,7 @@ { if (GET_MODE (operands[0]) == SImode) emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); - else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) + else if (GET_MODE (operands[0]) == DImode) emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); else FAIL; @@ -10509,7 +9565,7 @@ (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:DI 3 "=X,&1,&?d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_ZARCH" + "" { if (which_alternative != 0) return "#"; @@ -10589,19 +9645,9 @@ { operands[0] = force_reg (Pmode, operands[0]); if (TARGET_CPU_Z10) - { - if (TARGET_64BIT) - emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); - else - emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); - } + emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); else - { - if (TARGET_64BIT) - emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); - else - emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); - } + emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); DONE; } @@ -10610,25 +9656,12 @@ operands[0] = force_reg (Pmode, operands[0]); rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); if (TARGET_CPU_Z10) - { - if (TARGET_64BIT) - emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], - label_ref)); - else - emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], - label_ref)); - } + emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], + label_ref)); else - { - if (TARGET_64BIT) - emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], - label_ref, - force_reg (Pmode, label_ref))); - else - emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], - label_ref, - force_reg (Pmode, label_ref))); - } + emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], + label_ref, + force_reg (Pmode, label_ref))); DONE; } }) @@ -10652,9 +9685,9 @@ (set_attr "type" "branch") (set_attr "atype" "agen")]) -(define_insn "indirect_jump_via_thunk<mode>_z10" +(define_insn "indirect_jump_via_thunkdi_z10" [(set (pc) - (match_operand:P 0 "register_operand" "a"))] + (match_operand:DI 0 "register_operand" "a"))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK && TARGET_CPU_Z10" { @@ -10669,10 +9702,10 @@ (set_attr "type" "branch") (set_attr "atype" "agen")]) -(define_insn "indirect_jump_via_thunk<mode>" +(define_insn "indirect_jump_via_thunkdi" [(set (pc) - (match_operand:P 0 "register_operand" " a")) - (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] + (match_operand:DI 0 "register_operand" " a")) + (clobber (reg:DI INDIRECT_BRANCH_THUNK_REGNUM))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK && !TARGET_CPU_Z10" { @@ -10691,12 +9724,12 @@ ; The label_ref is wrapped into an if_then_else in order to hide it ; from mark_jump_label. Without this the label_ref would become the ; ONLY jump target of that jump breaking the control flow graph. -(define_insn "indirect_jump_via_inlinethunk<mode>_z10" - [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") +(define_insn "indirect_jump_via_inlinethunkdi_z10" + [(unspec [(if_then_else (match_operand:DI 1 "larl_operand" "X") (const_int 0) (const_int 0)) (const_int 0)] UNSPEC_EXECUTE_JUMP) - (set (pc) (match_operand:P 0 "register_operand" "a"))] + (set (pc) (match_operand:DI 0 "register_operand" "a"))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK && TARGET_CPU_Z10" { @@ -10707,12 +9740,12 @@ (set_attr "type" "branch") (set_attr "length" "10")]) -(define_insn "indirect_jump_via_inlinethunk<mode>" - [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") +(define_insn "indirect_jump_via_inlinethunkdi" + [(unspec [(if_then_else (match_operand:DI 1 "larl_operand" "X") (const_int 0) (const_int 0)) - (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) - (set (pc) (match_operand:P 0 "register_operand" "a"))] + (match_operand:DI 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) + (set (pc) (match_operand:DI 0 "register_operand" "a"))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK && !TARGET_CPU_Z10" { @@ -10753,23 +9786,9 @@ operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); if (TARGET_CPU_Z10) - { - if (TARGET_64BIT) - emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], - operands[1])); - else - emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], - operands[1])); - } + emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], operands[1])); else - { - if (TARGET_64BIT) - emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], - operands[1])); - else - emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], - operands[1])); - } + emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], operands[1])); DONE; } @@ -10778,29 +9797,14 @@ operands[0] = force_reg (Pmode, operands[0]); rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); if (TARGET_CPU_Z10) - { - if (TARGET_64BIT) - emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], - operands[1], - label_ref)); - else - emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], - operands[1], - label_ref)); - } - else - { - if (TARGET_64BIT) - emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], + emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], operands[1], - label_ref, - force_reg (Pmode, label_ref))); - else - emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], - operands[1], - label_ref, - force_reg (Pmode, label_ref))); - } + label_ref)); + else + emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], + operands[1], + label_ref, + force_reg (Pmode, label_ref))); DONE; } }) @@ -10824,8 +9828,8 @@ (set_attr "type" "branch") (set_attr "atype" "agen")]) -(define_insn "casesi_jump_via_thunk<mode>_z10" - [(set (pc) (match_operand:P 0 "register_operand" "a")) +(define_insn "casesi_jump_via_thunkdi_z10" + [(set (pc) (match_operand:DI 0 "register_operand" "a")) (use (label_ref (match_operand 1 "" "")))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK && TARGET_CPU_Z10" @@ -10841,10 +9845,10 @@ (set_attr "type" "branch") (set_attr "atype" "agen")]) -(define_insn "casesi_jump_via_thunk<mode>" - [(set (pc) (match_operand:P 0 "register_operand" "a")) +(define_insn "casesi_jump_via_thunkdi" + [(set (pc) (match_operand:DI 0 "register_operand" "a")) (use (label_ref (match_operand 1 "" ""))) - (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] + (clobber (reg:DI INDIRECT_BRANCH_THUNK_REGNUM))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK && !TARGET_CPU_Z10" { @@ -10863,12 +9867,12 @@ ; The label_ref is wrapped into an if_then_else in order to hide it ; from mark_jump_label. Without this the label_ref would become the ; ONLY jump target of that jump breaking the control flow graph. -(define_insn "casesi_jump_via_inlinethunk<mode>_z10" - [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") +(define_insn "casesi_jump_via_inlinethunkdi_z10" + [(unspec [(if_then_else (match_operand:DI 2 "larl_operand" "X") (const_int 0) (const_int 0)) (const_int 0)] UNSPEC_EXECUTE_JUMP) - (set (pc) (match_operand:P 0 "register_operand" "a")) + (set (pc) (match_operand:DI 0 "register_operand" "a")) (use (label_ref (match_operand 1 "" "")))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK && TARGET_CPU_Z10" @@ -10880,12 +9884,12 @@ (set_attr "type" "cs") (set_attr "length" "10")]) -(define_insn "casesi_jump_via_inlinethunk<mode>" - [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") +(define_insn "casesi_jump_via_inlinethunkdi" + [(unspec [(if_then_else (match_operand:DI 2 "larl_operand" "X") (const_int 0) (const_int 0)) - (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) - (set (pc) (match_operand:P 0 "register_operand" "a")) + (match_operand:DI 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) + (set (pc) (match_operand:DI 0 "register_operand" "a")) (use (label_ref (match_operand 1 "" "")))] "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK && !TARGET_CPU_Z10" @@ -10919,10 +9923,7 @@ if (GET_CODE (index) != REG) index = copy_to_mode_reg (Pmode, index); - if (TARGET_64BIT) - emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); - else - emit_insn (gen_ashlsi3 (index, index, const2_rtx)); + emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); @@ -11167,10 +10168,10 @@ (set_attr "atype" "agen") (set_attr "z196prop" "z196_cracked")]) -(define_insn "*basr_via_thunk<mode>_z10" - [(call (mem:QI (match_operand:P 0 "register_operand" "a")) +(define_insn "*basr_via_thunkdi_z10" + [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) (match_operand 1 "const_int_operand" "n")) - (clobber (match_operand:P 2 "register_operand" "=&r"))] + (clobber (match_operand:DI 2 "register_operand" "=&r"))] "TARGET_INDIRECT_BRANCH_NOBP_CALL && TARGET_CPU_Z10 && !SIBLING_CALL_P (insn)" @@ -11187,11 +10188,11 @@ (set_attr "atype" "agen") (set_attr "z196prop" "z196_cracked")]) -(define_insn "*basr_via_thunk<mode>" - [(call (mem:QI (match_operand:P 0 "register_operand" "a")) +(define_insn "*basr_via_thunkdi" + [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) (match_operand 1 "const_int_operand" "n")) - (clobber (match_operand:P 2 "register_operand" "=&r")) - (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] + (clobber (match_operand:DI 2 "register_operand" "=&r")) + (clobber (reg:DI INDIRECT_BRANCH_THUNK_REGNUM))] "TARGET_INDIRECT_BRANCH_NOBP_CALL && !TARGET_CPU_Z10 && !SIBLING_CALL_P (insn)" @@ -11302,7 +10303,7 @@ (call (mem:QI (match_operand 1 "register_operand" "a")) (match_operand 2 "const_int_operand" "n"))) (clobber (match_operand 3 "register_operand" "=&r")) - (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] + (clobber (reg:DI INDIRECT_BRANCH_THUNK_REGNUM))] "TARGET_INDIRECT_BRANCH_NOBP_CALL && !TARGET_CPU_Z10 && !SIBLING_CALL_P (insn) @@ -11324,15 +10325,15 @@ ;;- Thread-local storage support. ;; -(define_expand "@get_thread_pointer<mode>" - [(set (match_operand:P 0 "nonimmediate_operand" "") - (unspec:P [(reg:P TP_REGNUM)] UNSPEC_GET_TP))] +(define_expand "get_thread_pointerdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (unspec:DI [(reg:DI TP_REGNUM)] UNSPEC_GET_TP))] "" "") -(define_expand "set_thread_pointer<mode>" - [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) - (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] +(define_expand "set_thread_pointerdi" + [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) + (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] "" "") @@ -11348,25 +10349,11 @@ (unspec:DI [(match_operand:DI 1 "memory_operand" "T") (match_operand:DI 2 "" "")] UNSPEC_TLS_LOAD))] - "TARGET_64BIT" + "" "lg\t%0,%1%J2" [(set_attr "op_type" "RXE") (set_attr "z10prop" "z10_fwd_A3")]) -(define_insn "*tls_load_31" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") - (match_operand:SI 2 "" "")] - UNSPEC_TLS_LOAD))] - "!TARGET_64BIT" - "@ - l\t%0,%1%J2 - ly\t%0,%1%J2" - [(set_attr "op_type" "RX,RXY") - (set_attr "type" "load") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) - (define_insn "*bras_tls" [(set (match_operand 0 "" "") (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) @@ -11474,33 +10461,16 @@ if (<MODE>mode == TImode) emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); - else if (<MODE>mode == DImode && !TARGET_ZARCH) - emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); else emit_move_insn (operands[0], operands[1]); DONE; }) -; Different from movdi_31 in that we want no splitters. -(define_insn "atomic_loaddi_1" - [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") - (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] - UNSPEC_MOVA))] - "!TARGET_ZARCH" - "@ - lm\t%0,%M0,%S1 - lmy\t%0,%M0,%S1 - ld\t%0,%1 - ldy\t%0,%1" - [(set_attr "op_type" "RS,RSY,RS,RSY") - (set_attr "cpu_facility" "*,longdisp,*,longdisp") - (set_attr "type" "lm,lm,floaddf,floaddf")]) - (define_insn "atomic_loadti_1" [(set (match_operand:TI 0 "register_operand" "=r") (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] UNSPEC_MOVA))] - "TARGET_ZARCH" + "" "lpq\t%0,%1" [(set_attr "op_type" "RXY") (set_attr "type" "other")]) @@ -11519,8 +10489,6 @@ if (<MODE>mode == TImode) emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); - else if (<MODE>mode == DImode && !TARGET_ZARCH) - emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); else emit_move_insn (operands[0], operands[1]); if (is_mm_seq_cst (model)) @@ -11528,26 +10496,11 @@ DONE; }) -; Different from movdi_31 in that we want no splitters. -(define_insn "atomic_storedi_1" - [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") - (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] - UNSPEC_MOVA))] - "!TARGET_ZARCH" - "@ - stm\t%1,%N1,%S0 - stmy\t%1,%N1,%S0 - std %1,%0 - stdy %1,%0" - [(set_attr "op_type" "RS,RSY,RS,RSY") - (set_attr "cpu_facility" "*,longdisp,*,longdisp") - (set_attr "type" "stm,stm,fstoredf,fstoredf")]) - (define_insn "atomic_storeti_1" [(set (match_operand:TI 0 "memory_operand" "=T") (unspec:TI [(match_operand:TI 1 "register_operand" "r")] UNSPEC_MOVA))] - "TARGET_ZARCH" + "" "stpq\t%1,%0" [(set_attr "op_type" "RXY") (set_attr "type" "other")]) @@ -11577,13 +10530,13 @@ (define_expand "atomic_compare_and_swap<mode>_internal" [(parallel - [(set (match_operand:DGPR 0 "register_operand") - (match_operand:DGPR 1 "s_operand")) + [(set (match_operand:TDSI 0 "register_operand") + (match_operand:TDSI 1 "s_operand")) (set (match_dup 1) - (unspec_volatile:DGPR + (unspec_volatile:TDSI [(match_dup 1) - (match_operand:DGPR 2 "register_operand") - (match_operand:DGPR 3 "register_operand")] + (match_operand:TDSI 2 "register_operand") + (match_operand:TDSI 3 "register_operand")] UNSPECV_CAS)) (set (match_operand 4 "cc_reg_operand") (match_dup 5))])] @@ -11606,33 +10559,11 @@ UNSPECV_CAS)) (set (reg CC_REGNUM) (compare (match_dup 1) (match_dup 2)))] - "TARGET_ZARCH - && s390_match_ccmode (insn, CCZ1mode)" + "s390_match_ccmode (insn, CCZ1mode)" "c<td>sg\t%0,%3,%S1" [(set_attr "op_type" "RSY") (set_attr "type" "sem")]) -; cds, cdsy -(define_insn "*atomic_compare_and_swapdi_2" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) - (set (match_dup 1) - (unspec_volatile:DI - [(match_dup 1) - (match_operand:DI 2 "register_operand" "0,0") - (match_operand:DI 3 "register_operand" "r,r")] - UNSPECV_CAS)) - (set (reg CC_REGNUM) - (compare (match_dup 1) (match_dup 2)))] - "!TARGET_ZARCH - && s390_match_ccmode (insn, CCZ1mode)" - "@ - cds\t%0,%3,%S1 - cdsy\t%0,%3,%S1" - [(set_attr "op_type" "RS,RSY") - (set_attr "cpu_facility" "*,longdisp") - (set_attr "type" "sem")]) - ; cs, csy (define_insn "*atomic_compare_and_swapsi_3" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -11660,10 +10591,10 @@ ; z196 load and add, xor, or and and instructions (define_expand "atomic_fetch_<atomic><mode>" - [(match_operand:GPR 0 "register_operand") ;; val out - (ATOMIC_Z196:GPR - (match_operand:GPR 1 "memory_operand") ;; memory - (match_operand:GPR 2 "register_operand")) ;; val in + [(match_operand:DSI 0 "register_operand") ;; val out + (ATOMIC_Z196:DSI + (match_operand:DSI 1 "memory_operand") ;; memory + (match_operand:DSI 2 "register_operand")) ;; val in (match_operand:SI 3 "const_int_operand")] ;; model "TARGET_Z196" { @@ -11677,12 +10608,12 @@ ; lan, lang, lao, laog, lax, laxg, laa, laag (define_insn "atomic_fetch_<atomic><mode>_iaf" - [(set (match_operand:GPR 0 "register_operand" "=d") - (match_operand:GPR 1 "memory_operand" "+S")) + [(set (match_operand:DSI 0 "register_operand" "=d") + (match_operand:DSI 1 "memory_operand" "+S")) (set (match_dup 1) - (unspec_volatile:GPR - [(ATOMIC_Z196:GPR (match_dup 1) - (match_operand:GPR 2 "general_operand" "d"))] + (unspec_volatile:DSI + [(ATOMIC_Z196:DSI (match_dup 1) + (match_operand:DSI 2 "general_operand" "d"))] UNSPECV_ATOMIC_OP)) (clobber (reg:CC CC_REGNUM))] "TARGET_Z196" @@ -11747,10 +10678,8 @@ if (<MODE>mode == HImode || <MODE>mode == QImode) s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], false); - else if (<MODE>mode == SImode || TARGET_ZARCH) - s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); else - FAIL; + s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); DONE; }) @@ -11782,10 +10711,10 @@ DONE; }) -(define_expand "@probe_stack2<mode>" +(define_expand "probe_stack2di" [(set (reg:CCZ CC_REGNUM) - (compare:CCZ (reg:W 0) - (match_operand:W 0 "memory_operand"))) + (compare:CCZ (reg:DI 0) + (match_operand:DI 0 "memory_operand"))) (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] "") @@ -11793,7 +10722,7 @@ [(match_operand 0 "memory_operand")] "" { - emit_insn (gen_probe_stack2 (word_mode, operands[0])); + emit_insn (gen_probe_stack2di (operands[0])); DONE; }) @@ -12091,17 +11020,14 @@ if (!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) { - if (TARGET_64BIT) - emit_jump_insn (gen_returndi_prez10 (operands[0])); - else - emit_jump_insn (gen_returnsi_prez10 (operands[0])); + emit_jump_insn (gen_returndi_prez10 (operands[0])); DONE; } }) -(define_insn "*return<mode>" +(define_insn "*returndi" [(return) - (use (match_operand:P 0 "register_operand" "a"))] + (use (match_operand:DI 0 "register_operand" "a"))] "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" { if (TARGET_INDIRECT_BRANCH_NOBP_RET) @@ -12126,10 +11052,10 @@ (set_attr "type" "jsr") (set_attr "atype" "agen")]) -(define_insn "return<mode>_prez10" +(define_insn "returndi_prez10" [(return) - (use (match_operand:P 0 "register_operand" "a")) - (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] + (use (match_operand:DI 0 "register_operand" "a")) + (clobber (reg:DI INDIRECT_BRANCH_THUNK_REGNUM))] "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" { if (TARGET_INDIRECT_BRANCH_NOBP_RET) @@ -12161,7 +11087,7 @@ (define_expand "ptr_extend" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r"))] - "TARGET_64BIT" + "TARGET_TPF" { emit_insn (gen_anddi3 (operands[0], gen_lowpart (DImode, operands[1]), @@ -12184,9 +11110,9 @@ ; Stack Protector Patterns ; -(define_insn "stack_protect_global_guard_addr<mode>" - [(set (match_operand:P 0 "register_operand" "=d") - (unspec_volatile:P [(const_int 0)] UNSPECV_SP_GLOBAL_GUARD_ADDR))] +(define_insn "stack_protect_global_guard_addrdi" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec_volatile:DI [(const_int 0)] UNSPECV_SP_GLOBAL_GUARD_ADDR))] "" { if (flag_s390_stack_protector_guard_record) @@ -12194,37 +11120,29 @@ if (flag_pic) { if (TARGET_Z10) - output_asm_insn ("l<g>rl\t%0,__stack_chk_guard@GOTENT", operands); + output_asm_insn ("lgrl\t%0,__stack_chk_guard@GOTENT", operands); else { output_asm_insn ("larl\t%0,__stack_chk_guard@GOTENT", operands); - output_asm_insn ("l<g>\t%0,0(%0)", operands); + output_asm_insn ("lg\t%0,0(%0)", operands); } } else output_asm_insn ("larl\t%0,__stack_chk_guard", operands); if (flag_s390_stack_protector_guard_record) fprintf (asm_out_file, "\t.section __stack_protector_loc,\\"a\\",@progbits\n" - "\t.%s 1b\n" - "\t.previous\n", TARGET_64BIT ? "quad" : "long"); + "\t.quad 1b\n" + "\t.previous\n"); return ""; } [(set (attr "mnemonic") - (cond [(match_test "flag_pic && TARGET_Z10") (const_string "l<g>rl") + (cond [(match_test "flag_pic && TARGET_Z10") (const_string "lgrl") (match_test "flag_pic && !TARGET_Z10") (const_string "*")] (const_string "larl")))]) -; Insns stack_protect_get_tp{si,di} are similar to *get_tp_{31,64} but still -; distinct in the sense that they force recomputation of the thread pointer -; instead of potentially reloading it from stack. - -(define_insn_and_split "stack_protect_get_tpsi" - [(set (match_operand:SI 0 "register_operand" "=d") - (unspec_volatile:SI [(const_int 0)] UNSPECV_SP_GET_TP))] - "" - "#" - "&& reload_completed" - [(set (match_dup 0) (reg:SI AR0_REGNUM))]) +; Insn stack_protect_get_tpdi is similar to *get_tp_64 but still distinct in +; the sense that it forces recomputation of the thread pointer instead of +; potentially reloading it from stack. (define_insn_and_split "stack_protect_get_tpdi" [(set (match_operand:DI 0 "register_operand" "=d") @@ -12245,36 +11163,27 @@ if (TARGET_SP_GLOBAL_GUARD) { rtx addr = gen_reg_rtx (Pmode); - if (TARGET_64BIT) - emit_insn (gen_stack_protect_global_guard_addrdi (addr)); - else - emit_insn (gen_stack_protect_global_guard_addrsi (addr)); + emit_insn (gen_stack_protect_global_guard_addrdi (addr)); operands[1] = gen_rtx_MEM (Pmode, addr); } else { #ifdef TARGET_THREAD_SSP_OFFSET rtx tp = gen_reg_rtx (Pmode); - if (TARGET_64BIT) - emit_insn (gen_stack_protect_get_tpdi (tp)); - else - emit_insn (gen_stack_protect_get_tpsi (tp)); + emit_insn (gen_stack_protect_get_tpdi (tp)); operands[1] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET))); #endif } - if (TARGET_64BIT) - emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); - else - emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); + emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); DONE; }) -(define_insn "stack_protect_set<mode>" - [(set (match_operand:DSI 0 "memory_operand" "=Q") - (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] +(define_insn "stack_protect_setdi" + [(set (match_operand:DI 0 "memory_operand" "=Q") + (unspec:DI [(match_operand:DI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] "" "mvc\t%O0(%G0,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -12290,29 +11199,20 @@ if (TARGET_SP_GLOBAL_GUARD) { rtx addr = gen_reg_rtx (Pmode); - if (TARGET_64BIT) - emit_insn (gen_stack_protect_global_guard_addrdi (addr)); - else - emit_insn (gen_stack_protect_global_guard_addrsi (addr)); + emit_insn (gen_stack_protect_global_guard_addrdi (addr)); operands[1] = gen_rtx_MEM (Pmode, addr); } else { #ifdef TARGET_THREAD_SSP_OFFSET rtx tp = gen_reg_rtx (Pmode); - if (TARGET_64BIT) - emit_insn (gen_stack_protect_get_tpdi (tp)); - else - emit_insn (gen_stack_protect_get_tpsi (tp)); + emit_insn (gen_stack_protect_get_tpdi (tp)); operands[1] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET))); #endif } - if (TARGET_64BIT) - emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); - else - emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); + emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); @@ -12320,10 +11220,10 @@ DONE; }) -(define_insn "stack_protect_test<mode>" +(define_insn "stack_protect_testdi" [(set (reg:CCZ CC_REGNUM) - (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") - (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] + (unspec:CCZ [(match_operand:DI 0 "memory_operand" "Q") + (match_operand:DI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] "" "clc\t%O0(%G0,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -12331,10 +11231,10 @@ ; This is used in s390_emit_prologue in order to prevent insns ; adjusting the stack pointer to be moved over insns writing stack ; slots using a copy of the stack pointer in a different register. -(define_insn "@stack_tie<mode>" +(define_insn "stack_tiedi" [(set (match_operand:BLK 0 "memory_operand" "+m") (unspec:BLK [(match_dup 0) - (match_operand:P 1 "register_operand" "r")] UNSPEC_TIE))] + (match_operand:DI 1 "register_operand" "r")] UNSPEC_TIE))] "" "" [(set_attr "length" "0")]) @@ -12389,8 +11289,8 @@ ; may overlap. ; lrvr, lrv, strv, lrvgr, lrvg, strvg (define_insn "bswap<mode>2" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") - (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] + [(set (match_operand:DSI 0 "nonimmediate_operand" "=d,d,T") + (bswap:DSI (match_operand:DSI 1 "nonimmediate_operand" " d,T,d")))] "" "@ lrv<g>r\t%0,%1 @@ -12924,15 +11824,12 @@ "" { /* Offset from thread pointer to __private_ss. */ - int psso = TARGET_64BIT ? 0x38 : 0x20; + int psso = 0x38; rtx tp = s390_get_thread_pointer (); rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); rtx reg = gen_reg_rtx (Pmode); rtx cc; - if (TARGET_64BIT) - emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); - else - emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); + emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); cc = s390_emit_compare (VOIDmode, GT, reg, guard); s390_emit_jump (operands[1], cc); @@ -12953,11 +11850,11 @@ ; allow the edge to the BB with the call done label to be ; redirected both need to make use of the same label_ref. -(define_insn "@split_stack_call<mode>" +(define_insn "split_stack_calldi" [(set (pc) (label_ref (match_operand 2 "" ""))) ; call done label - (set (reg:P 1) (unspec_volatile:P [(match_operand 0 "bras_sym_operand" "X") - (reg:P 1)] - UNSPECV_SPLIT_STACK_CALL)) + (set (reg:DI 1) (unspec_volatile:DI [(match_operand 0 "bras_sym_operand" "X") + (reg:DI 1)] + UNSPECV_SPLIT_STACK_CALL)) (use (label_ref (match_operand 1 "" "X"))) ; parm block label (use (match_operand 3 "const_int_operand" "X")) ; frame size (use (match_operand 4 "const_int_operand" "X"))] ; arg size @@ -12971,14 +11868,14 @@ ; As above but with a conditional jump -(define_insn "@split_stack_cond_call<mode>" +(define_insn "split_stack_cond_calldi" [(set (pc) (if_then_else (match_operand 5 "" "") ; condition (label_ref (match_operand 2 "" "")) ; call done label (pc))) - (set (reg:P 1) (unspec_volatile:P [(match_operand 0 "bras_sym_operand" "X") - (reg:P 1)] + (set (reg:DI 1) (unspec_volatile:DI [(match_operand 0 "bras_sym_operand" "X") + (reg:DI 1)] UNSPECV_SPLIT_STACK_CALL)) (use (label_ref (match_operand 1 "" "X"))) ; parm block label (use (match_operand 3 "const_int_operand" "X")) ; frame size diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt index 93bd55a07e9d..687bad5ec2d5 100644 --- a/gcc/config/s390/s390.opt +++ b/gcc/config/s390/s390.opt @@ -44,11 +44,13 @@ Variable long s390_cost_pointer m31 -Target RejectNegative Negative(m64) InverseMask(64BIT) -31 bit ABI. +Target Var(flag_m31) Undocumented +; After removing -m31, -m64 is the only supported ABI. +; Therefore, specifying -m64 doesn't have any additional effect. +; However, keep it for backwards compatibility. m64 -Target RejectNegative Negative(m31) Mask(64BIT) +Target Ignore 64 bit ABI. march= @@ -139,7 +141,7 @@ Target Mask(DEBUG_ARG) Save Additional debug prints. mesa -Target RejectNegative Negative(mzarch) InverseMask(ZARCH) +Target Var(flag_mesa) Undocumented ESA/390 architecture. mhard-dfp @@ -243,8 +245,11 @@ mwarn-framesize= Target RejectNegative Joined UInteger Var(s390_warn_framesize) Save Warn if a single function's framesize exceeds the given framesize. +; After removing ESA/390 support, z/Architecture is the only supported +; cpu mode. Therefore, specifying -mzarch doesn't have any additional +; effect. However, keep it for backwards compatibility. mzarch -Target RejectNegative Negative(mesa) Mask(ZARCH) +Target Ignore z/Architecture. ; This option was added to fix some testsuite failures. diff --git a/gcc/config/s390/s390.opt.urls b/gcc/config/s390/s390.opt.urls index 77dccc463aa4..1e214feb3a55 100644 --- a/gcc/config/s390/s390.opt.urls +++ b/gcc/config/s390/s390.opt.urls @@ -1,8 +1,5 @@ ; Autogenerated by regenerate-opt-urls.py from gcc/config/s390/s390.opt and generated HTML -m31 -UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-m31) - m64 UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-m64-2) @@ -15,9 +12,6 @@ UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-mbackchain) mdebug UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-mdebug-1) -mesa -UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-mesa) - mhard-dfp UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-mhard-dfp-1) diff --git a/gcc/config/s390/s390x.h b/gcc/config/s390/s390x.h deleted file mode 100644 index 1c25d2d5c2f1..000000000000 --- a/gcc/config/s390/s390x.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Definitions of target machine for IBM zSeries 64-bit - Copyright (C) 2002-2026 Free Software Foundation, Inc. - Contributed by Hartmut Penner ([email protected]) and - Ulrich Weigand ([email protected]). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#ifndef _S390X_H -#define _S390X_H - -#define DEFAULT_TARGET_64BIT - -#endif diff --git a/gcc/config/s390/t-linux64 b/gcc/config/s390/t-linux64 index cc6ab367072f..1e5d6789a2ce 100644 --- a/gcc/config/s390/t-linux64 +++ b/gcc/config/s390/t-linux64 @@ -2,10 +2,12 @@ # are found in /lib32 and /usr/lib32, /lib64 and /usr/lib64 are symlinks to # /lib and /usr/lib, while other distributions install libraries into /lib64 # and /usr/lib64. The LSB does not enforce the use of /lib64 and /usr/lib64, -# it doesn't tell anything about the 32bit libraries on those systems. Set -# MULTILIB_OSDIRNAMES according to what is found on the target. +# it doesn't tell anything about the 32bit libraries on those systems. -MULTILIB_OPTIONS = m64/m31 -MULTILIB_DIRNAMES = 64 32 +# After the removal of -m31 there is only one ABI left which means multilib +# support is not needed anymore. Still maintain the directory structure for +# 64-bit s390x which means library directories are named lib64. + +MULTILIB_OPTIONS = m64 +MULTILIB_DIRNAMES = 64 MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu) -MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu) diff --git a/gcc/config/s390/tpf.h b/gcc/config/s390/tpf.h index ca7440d5563c..149ce703976c 100644 --- a/gcc/config/s390/tpf.h +++ b/gcc/config/s390/tpf.h @@ -41,6 +41,8 @@ along with GCC; see the file COPYING3. If not see #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 32 +/* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ +#define POINTERS_EXTEND_UNSIGNED -1 /* TPF OS specific stack-pointer offset. */ #undef STACK_POINTER_OFFSET @@ -49,8 +51,7 @@ along with GCC; see the file COPYING3. If not see /* When building for TPF, set a generic default target that is 64 bits. Also enable TPF profiling support and the standard backchain by default. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_TPF_PROFILING | MASK_64BIT | MASK_ZARCH \ - | MASK_HARD_DFP | MASK_BACKCHAIN) +#define TARGET_DEFAULT (MASK_TPF_PROFILING | MASK_HARD_DFP | MASK_BACKCHAIN) /* Exception handling. */ @@ -93,7 +94,7 @@ along with GCC; see the file COPYING3. If not see make it work with older binutils. */ #undef ASM_SPEC #define ASM_SPEC \ - "%{m31&m64}%{mesa&mzarch}%{march=z*}" \ + "%{march=z*}" \ "%{march=arch5:-march=z900}" \ "%{march=arch6:-march=z990}" \ "%{march=arch7:-march=z9-ec}" \ diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index f0be6f10c1ac..b65c52a95f9f 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -358,7 +358,7 @@ (define_split [(set (match_operand:V_128 0 "register_operand" "") (match_operand:V_128 1 "memory_operand" ""))] - "TARGET_ZARCH && reload_completed + "reload_completed && !VECTOR_REG_P (operands[0]) && !s_operand (operands[1], VOIDmode)" [(set (match_dup 0) (match_dup 1))] @@ -473,7 +473,7 @@ "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, v, Q, Q, d, d,f,d,d,d,d,T,b") (match_operand:V_64 1 "general_operand" " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,jzz,j00,jm1,j00,jm1,d,f,b,d,T,d,d"))] - "TARGET_ZARCH" + "" "@ ldr\t%0,%1 ld\t%0,%1 @@ -3183,7 +3183,7 @@ ; operand in a VR, therefore load it into a FPR pair first. (define_expand "floatuns<mode>tf2_vr" [(set (match_dup 2) - (unsigned_float:FPRX2 (match_operand:GPR 1 "register_operand" ""))) + (unsigned_float:FPRX2 (match_operand:DSI 1 "register_operand" ""))) (set (match_operand:TF 0 "register_operand" "") (subreg:TF (match_dup 2) 0))] "TARGET_VXE" @@ -3193,7 +3193,7 @@ (define_expand "floatuns<mode>tf2" [(match_operand:TF 0 "register_operand" "") - (match_operand:GPR 1 "register_operand" "")] + (match_operand:DSI 1 "register_operand" "")] "HAVE_TF (floatuns<mode>tf2)" { EXPAND_TF (floatuns<mode>tf2, 2); }) @@ -3214,9 +3214,9 @@ (define_expand "fix_trunctf<mode>2_vr" [(set (match_dup 2) (unspec:FPRX2 [(match_operand:TF 1 "register_operand")] UNSPEC_TF_TO_FPRX2)) - (parallel [(set (match_operand:GPR 0 "register_operand" "") - (fix:GPR (match_dup 2))) - (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) + (parallel [(set (match_operand:DSI 0 "register_operand" "") + (fix:DSI (match_dup 2))) + (unspec:DSI [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "TARGET_VXE" { @@ -3224,7 +3224,7 @@ }) (define_expand "fix_trunctf<mode>2" - [(match_operand:GPR 0 "register_operand" "") + [(match_operand:DSI 0 "register_operand" "") (match_operand:TF 1 "register_operand" "")] "HAVE_TF (fix_trunctf<mode>2)" { EXPAND_TF (fix_trunctf<mode>2, 2); }) @@ -3246,9 +3246,9 @@ (define_expand "fixuns_trunctf<mode>2_vr" [(set (match_dup 2) (unspec:FPRX2 [(match_operand:TF 1 "register_operand")] UNSPEC_TF_TO_FPRX2)) - (parallel [(set (match_operand:GPR 0 "register_operand" "") - (unsigned_fix:GPR (match_dup 2))) - (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) + (parallel [(set (match_operand:DSI 0 "register_operand" "") + (unsigned_fix:DSI (match_dup 2))) + (unspec:DSI [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) (clobber (reg:CC CC_REGNUM))])] "TARGET_VXE" { @@ -3256,7 +3256,7 @@ }) (define_expand "fixuns_trunctf<mode>2" - [(match_operand:GPR 0 "register_operand" "") + [(match_operand:DSI 0 "register_operand" "") (match_operand:TF 1 "register_operand" "")] "HAVE_TF (fixuns_trunctf<mode>2)" { EXPAND_TF (fixuns_trunctf<mode>2, 2); }) @@ -3566,7 +3566,7 @@ (match_operand:QI 3 "register_operand") (match_operand:QI 4 "vll_bias_operand") ] - "TARGET_VX && TARGET_64BIT" + "TARGET_VX" { rtx mem = adjust_address (operands[1], BLKmode, 0); @@ -3582,7 +3582,7 @@ (match_operand:QI 2 "register_operand") (match_operand:QI 3 "vll_bias_operand") ] - "TARGET_VX && TARGET_64BIT" + "TARGET_VX" { rtx mem = adjust_address (operands[0], BLKmode, 0); diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index a5cac359c1cd..6d06f1a7915a 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -435,8 +435,6 @@ ; Vector scatter element ; vscef, vsceg - -; A 64 bit target address generated from 32 bit elements (define_insn "vec_scatter_element<V_HW_4:mode>_DI" [(set (mem:<non_vec> (plus:DI (zero_extend:DI @@ -447,27 +445,10 @@ (vec_select:<non_vec> (match_operand:V_HW_4 0 "register_operand" "v") (parallel [(match_dup 3)])))] - "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4" + "TARGET_VX && UINTVAL (operands[3]) < 4" "vscef\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) -; A 31 bit target address is generated from 64 bit elements -; vsceg -(define_insn "vec_scatter_element<V_HW_2:mode>_SI" - [(set (mem:<non_vec> - (plus:SI (subreg:SI - (vec_select:<non_vec_int> - (match_operand:<TOINTVEC> 1 "register_operand" "v") - (parallel [(match_operand:QI 3 "const_mask_operand" "C")])) 4) - (match_operand:SI 2 "address_operand" "ZQ"))) - (vec_select:<non_vec> - (match_operand:V_HW_2 0 "register_operand" "v") - (parallel [(match_dup 3)])))] - "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_2:MODE>mode)" - "vsce<V_HW_2:bhfgq>\t%v0,%O2(%v1,%R2),%3" - [(set_attr "op_type" "VRV")]) - -; Element size and target address size is the same ; vscef, vsceg (define_insn "vec_scatter_element<mode>_<non_vec_int>" [(set (mem:<non_vec> @@ -483,33 +464,6 @@ "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) -; Depending on the address size we have to expand a different pattern. -; This however cannot be represented in s390-builtins.def so we do the -; multiplexing here in the expander. -(define_expand "vec_scatter_element<V_HW_32_64:mode>" - [(match_operand:V_HW_32_64 0 "register_operand" "") - (match_operand:<TOINTVEC> 1 "register_operand" "") - (match_operand 2 "address_operand" "") - (match_operand:QI 3 "const_mask_operand" "")] - "TARGET_VX" -{ - if (TARGET_64BIT) - { - PUT_MODE (operands[2], DImode); - emit_insn ( - gen_vec_scatter_element<V_HW_32_64:mode>_DI (operands[0], operands[1], - operands[2], operands[3])); - } - else - { - PUT_MODE (operands[2], SImode); - emit_insn ( - gen_vec_scatter_element<V_HW_32_64:mode>_SI (operands[0], operands[1], - operands[2], operands[3])); - } - DONE; -}) - ; Vector select diff --git a/gcc/configure b/gcc/configure index ceb51cb63dcd..cba5a9ecbd6a 100755 --- a/gcc/configure +++ b/gcc/configure @@ -28307,23 +28307,6 @@ x: .word 2 la.tls.gd a0,x call __tls_get_addr' ;; - s390-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -foo: .long 25 - .text - .long foo@TLSGD - .long foo@TLSLDM - .long foo@DTPOFF - .long foo@NTPOFF - .long foo@GOTNTPOFF - .long foo@INDNTPOFF - l %r1,foo@GOTNTPOFF(%r12) - l %r1,0(%r1):tls_load:foo - bas %r14,0(%r1,%r13):tls_gdcall:foo - bas %r14,0(%r1,%r13):tls_ldcall:foo' - tls_as_opt="-m31" - ;; s390x-*-*) conftest_s=' .section ".tdata","awT",@progbits @@ -31568,7 +31551,7 @@ $as_echo "#define HAVE_AS_16B_ATOMIC 1" >>confdefs.h fi ;; - s390*-*-*) + s390x-*-*) { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .gnu_attribute support" >&5 $as_echo_n "checking assembler for .gnu_attribute support... " >&6; } if ${gcc_cv_as_s390_gnu_attribute+:} false; then : @@ -33701,7 +33684,7 @@ fi case "$target" in powerpc*-*-linux* | \ sparc*-*-linux* | \ - s390*-*-linux* | \ + s390x-*-linux* | \ alpha*-*-linux*) # Check whether --with-long-double-128 was given. @@ -33710,7 +33693,7 @@ if test "${with_long_double_128+set}" = set; then : else case "$target" in - s390*-*-linux-musl*) + s390x-*-linux-musl*) gcc_cv_target_ldbl128=yes ;; powerpc*-*-linux-musl*) @@ -35076,7 +35059,7 @@ fi case $target in - s390*-linux*) + s390x-linux*) if test x"$enable_s390_excess_float_precision" = xauto; then # Can we autodetect the behavior of the target libc? if test "$target" = "$host" -a "$host" = "$build"; then diff --git a/gcc/configure.ac b/gcc/configure.ac index ccd1020413a5..6c560ceb90f4 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -4220,23 +4220,6 @@ x: .word 2 la.tls.gd a0,x call __tls_get_addr' ;; - s390-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -foo: .long 25 - .text - .long foo@TLSGD - .long foo@TLSLDM - .long foo@DTPOFF - .long foo@NTPOFF - .long foo@GOTNTPOFF - .long foo@INDNTPOFF - l %r1,foo@GOTNTPOFF(%r12) - l %r1,0(%r1):tls_load:foo - bas %r14,0(%r1,%r13):tls_gdcall:foo - bas %r14,0(%r1,%r13):tls_ldcall:foo' - tls_as_opt="-m31" - ;; s390x-*-*) conftest_s=' .section ".tdata","awT",@progbits @@ -5545,7 +5528,7 @@ x: [AC_DEFINE(HAVE_AS_16B_ATOMIC, 1, [Define if your assembler supports LSX and SCQ for 16B atomic.])]) ;; - s390*-*-*) + s390x-*-*) gcc_GAS_CHECK_FEATURE([.gnu_attribute support], gcc_cv_as_s390_gnu_attribute,, [.gnu_attribute 8,1],, @@ -6952,14 +6935,14 @@ AS_IF([test x$gcc_cv_sys_sdt_h = xyes], [ case "$target" in powerpc*-*-linux* | \ sparc*-*-linux* | \ - s390*-*-linux* | \ + s390x-*-linux* | \ alpha*-*-linux*) AC_ARG_WITH(long-double-128, [AS_HELP_STRING([--with-long-double-128], [use 128-bit long double by default])], gcc_cv_target_ldbl128="$with_long_double_128", [ case "$target" in - s390*-*-linux-musl*) + s390x-*-linux-musl*) gcc_cv_target_ldbl128=yes ;; powerpc*-*-linux-musl*) @@ -7804,7 +7787,7 @@ AC_ARG_ENABLE(s390-excess-float-precision, [],[enable_s390_excess_float_precision=auto]) case $target in - s390*-linux*) + s390x-linux*) if test x"$enable_s390_excess_float_precision" = xauto; then # Can we autodetect the behavior of the target libc? if test "$target" = "$host" -a "$host" = "$build"; then diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index aab839952a04..315210918777 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -879,7 +879,7 @@ mips64orion, mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2, mipsisa64r2el, mipsisa64sb1, mipsisa64sr71k, mipstx39, mmix, mn10300, moxie, msp430, nds32be, nds32le, nvptx, or1k, pdp11, powerpc, powerpc64, powerpc64le, powerpcle, pru, riscv32, riscv32be, riscv64, riscv64be, rl78, rx, -s390, s390x, sh, shle, sparc, sparc64, tic6x, v850, +s390x, sh, shle, sparc, sparc64, tic6x, v850, v850e, v850e1, vax, visium, x86_64, xstormy16, xtensa @end quotation @@ -2239,7 +2239,7 @@ you are building a bi-arch or multi-arch Binutils in a combined tree. On mips-linux, this will build a tri-arch compiler (ABI o32/n32/64), defaulted to o32. Currently, this option only affects sparc-linux, powerpc-linux, x86-linux, -mips-linux and s390-linux. +and mips-linux. @item --enable-default-pie Turn on @option{-fPIE} and @option{-pie} by default. @@ -2732,7 +2732,7 @@ target if target Binutils supported. @item --enable-s390-excess-float-precision @itemx --disable-s390-excess-float-precision -On s390(x) targets, enable treatment of float expressions with double precision +On s390x targets, enable treatment of float expressions with double precision when in standards-compliant mode (e.g., when @code{--std=c99} or @code{-fexcess-precision=standard} are given). diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4cdea7118423..606d666cd51b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1427,7 +1427,7 @@ See RS/6000 and PowerPC Options. -mlong-double-64 -mlong-double-128 -mbackchain -mpacked-stack -msmall-exec -mmvcle --m64 -m31 -mdebug -mesa -mzarch +-m64 -mdebug -mzarch -mhtm -mvx -mzvector -mtpf-trace -mtpf-trace-skip -mmain -mfused-madd -mno-fused-madd @@ -33232,29 +33232,19 @@ exceed 64k. The default is to use the @code{basr} instruction instead, which does not have this limitation. @opindex m64 -@opindex m31 @item -m64 -@itemx -m31 -When @option{-m31} is specified, generate code compliant to the -GNU/Linux for S/390 ABI@. When @option{-m64} is specified, generate -code compliant to the GNU/Linux for zSeries ABI@. This allows GCC in -particular to generate 64-bit instructions. For the @samp{s390} -targets, the default is @option{-m31}, while the @samp{s390x} -targets default to @option{-m64}. Note, @option{-m31} is deprecated and -support will be removed. +After the removal of @option{-m31}, option @option{-m64} has no counterpart +anymore. For the sake of backwards compatibility, the option is still accepted +but doesn't have any effect anymore. Therefore, generated code comprises +64-bit instructions and follows the GNU/Linux for zSeries ABI by default. + @opindex mzarch -@opindex mesa @item -mzarch -@itemx -mesa -When @option{-mzarch} is specified, generate code using the -instructions available on z/Architecture. -When @option{-mesa} is specified, generate code using the -instructions available on ESA/390. Note that @option{-mesa} is -not possible with @option{-m64}. -When generating code compliant to the GNU/Linux for S/390 ABI, -the default is @option{-mesa}. When generating code compliant -to the GNU/Linux for zSeries ABI, the default is @option{-mzarch}. +After the removal of @option{-mesa}, option @option{-mzarch} has no counterpart +anymore. For the sake of backwards compatibility, the option is still accepted +but doesn't have any effect anymore. Therefore, generated code comprises +instructions available on z/Architecture by default. @opindex mhtm @opindex mno-htm diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c index d3962bdc344c..ed86b446fedc 100644 --- a/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target arm*-*-* s390-*-* } } */ +/* { dg-do compile { target arm*-*-* } } */ /* { dg-options "-std=c99" } we need long long */ /* { dg-additional-options "-mcpu=unset -march=armv7-a+fp -marm" { target arm*-*-* } } */ @@ -7,9 +7,6 @@ #if defined (__arm__) # define GPR1 "{r4}" # define GPR2_RAW "r5" -#elif defined (__s390__) -# define GPR1 "{r4}" -# define GPR2_RAW "r5" #endif #define GPR2 "{"GPR2_RAW"}" diff --git a/gcc/testsuite/gcc.dg/builtin-bswap-8.c b/gcc/testsuite/gcc.dg/builtin-bswap-8.c index 3dbde6ba0ab4..35f2bd6b5d18 100644 --- a/gcc/testsuite/gcc.dg/builtin-bswap-8.c +++ b/gcc/testsuite/gcc.dg/builtin-bswap-8.c @@ -1,7 +1,6 @@ /* { dg-do compile { target arm*-*-* alpha*-*-* i?86-*-* powerpc*-*-* rs6000-*-* x86_64-*-* s390*-*-* } } */ /* { dg-require-effective-target stdint_types } */ /* { dg-options "-O2 -fdump-rtl-combine" } */ -/* { dg-options "-O2 -fdump-rtl-combine -march=z900" { target s390-*-* } } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.dg/ifcvt-4.c b/gcc/testsuite/gcc.dg/ifcvt-4.c index 485352df6e60..0a7b1b3fb665 100644 --- a/gcc/testsuite/gcc.dg/ifcvt-4.c +++ b/gcc/testsuite/gcc.dg/ifcvt-4.c @@ -4,7 +4,6 @@ /* { dg-additional-options "-mtune-ctrl=^one_if_conv_insn" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" { "arm*-*-* avr-*-* cris-*-* hppa*64*-*-* visium-*-*" riscv*-*-* msp430-*-* pru-*-* loongarch32-*-* } } */ /* { dg-skip-if "" { { sparc*-*-* } && { ! sparc_v9 } } } */ -/* { dg-skip-if "" { "s390x-*-*" } { "-m31" } } */ typedef int word __attribute__((mode(word))); diff --git a/gcc/testsuite/gcc.dg/optimize-bswaphi-1.c b/gcc/testsuite/gcc.dg/optimize-bswaphi-1.c index a5d8bfd5838a..286432cb4444 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswaphi-1.c +++ b/gcc/testsuite/gcc.dg/optimize-bswaphi-1.c @@ -2,7 +2,6 @@ /* { dg-require-effective-target bswap } */ /* { dg-require-effective-target stdint_types } */ /* { dg-options "-O2 -fdump-tree-bswap" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.dg/optimize-bswapsi-3.c b/gcc/testsuite/gcc.dg/optimize-bswapsi-3.c index 7cd1b406a871..44ab8ffa308b 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswapsi-3.c +++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-3.c @@ -2,7 +2,6 @@ /* { dg-require-effective-target bswap } */ /* { dg-require-effective-target stdint_types } */ /* { dg-options "-O2 -fdump-tree-optimized" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ typedef int SItype __attribute__ ((mode (SI))); typedef int DItype __attribute__ ((mode (DI))); diff --git a/gcc/testsuite/gcc.dg/optimize-bswapsi-4.c b/gcc/testsuite/gcc.dg/optimize-bswapsi-4.c index cfcc8324c574..35a1ff300c57 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswapsi-4.c +++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-4.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target bswap } */ /* { dg-options "-O2 -fdump-tree-bswap" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ typedef unsigned char u8; typedef unsigned int u32; diff --git a/gcc/testsuite/gcc.dg/optimize-bswapsi-5.c b/gcc/testsuite/gcc.dg/optimize-bswapsi-5.c index 5934aacf75a0..4651f276932c 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswapsi-5.c +++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-5.c @@ -1,7 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target bswap } */ /* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-optimized -fno-inline-functions" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ struct L { unsigned int l[2]; }; union U { double a; struct L l; } u; diff --git a/gcc/testsuite/gcc.dg/optimize-bswapsi-6.c b/gcc/testsuite/gcc.dg/optimize-bswapsi-6.c index 75f8aecb5d89..e850493e4902 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswapsi-6.c +++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-6.c @@ -2,7 +2,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target bswap } */ /* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-store-merging" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ typedef unsigned char u8; typedef unsigned int u32; diff --git a/gcc/testsuite/gcc.dg/optimize-bswapsi-7.c b/gcc/testsuite/gcc.dg/optimize-bswapsi-7.c index 1e4db5e48189..e3f71a32e5f5 100644 --- a/gcc/testsuite/gcc.dg/optimize-bswapsi-7.c +++ b/gcc/testsuite/gcc.dg/optimize-bswapsi-7.c @@ -2,7 +2,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target bswap } */ /* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-optimized" } */ -/* { dg-additional-options "-march=z900" { target s390-*-* } } */ static unsigned int f1 (unsigned int x) diff --git a/gcc/testsuite/gcc.dg/pr120525.c b/gcc/testsuite/gcc.dg/pr120525.c index 5ab7a2244dc2..7dc32e55ba5d 100644 --- a/gcc/testsuite/gcc.dg/pr120525.c +++ b/gcc/testsuite/gcc.dg/pr120525.c @@ -1,6 +1,5 @@ /* { dg-do compile { target fpic } } */ /* { dg-options "-O2 -fpic -g" } */ -/* { dg-additional-options "-m31" { target s390x-*-* } } */ typedef __SIZE_TYPE__ uintptr_t; static __thread uintptr_t start_sp; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c index a8f2c3bbfdb4..a43fd79fef72 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c @@ -5,11 +5,6 @@ /* { dg-options "-O1 -ftree-loop-ivcanon -funroll-loops -fdump-tree-ivcanon-details -fdump-tree-cunroll-details -fdump-tree-optimized -mshort-calls" {target epiphany-*-*} } */ -/* On 31-bit S/390 the function address will be stored (once) in the literal pool, - so scan-assembler-times "foo" will return 1 even if the loop is fully unrolled. - -msmall-exec avoids this by enabling a call instruction with immediate operand. */ -/* { dg-options "-O1 -ftree-loop-ivcanon -funroll-loops -fdump-tree-ivcanon-details -fdump-tree-cunroll-details -fdump-tree-optimized -msmall-exec" { target s390-*-* } } */ - /* On Darwin, we call extern functions via a stub in PIC mode which is default and the stub is named after the function. To avoid this we use -static to go out of PIC mode. */ diff --git a/gcc/testsuite/gcc.misc-tests/linkage.exp b/gcc/testsuite/gcc.misc-tests/linkage.exp index 1f9d6afb40ae..07e542e2ec3e 100644 --- a/gcc/testsuite/gcc.misc-tests/linkage.exp +++ b/gcc/testsuite/gcc.misc-tests/linkage.exp @@ -61,15 +61,6 @@ if { [isnative] && ![is_remote host] } then { if [ string match "*64*" $file_string ] { set native_cflags "-xarch=amd64" } - } - if [istarget "s390*-*-linux*"] { - set file_string [exec file "linkage-x.o"] - if [ string match "*32-bit*" $file_string ] { - set native_cflags "-m31" - } - if [ string match "*64-bit*" $file_string ] { - set native_cflags "-m64" - } } elseif {[istarget "i?86-*-linux*"] || [istarget "x86_64-*-linux*"] || [istarget "i?86-*-gnu*"] || [istarget "x86_64-*-gnu*"] } then { set file_string [exec file "linkage-x.o"] diff --git a/gcc/testsuite/gcc.target/s390/20020926-1.c b/gcc/testsuite/gcc.target/s390/20020926-1.c deleted file mode 100644 index aaa134276968..000000000000 --- a/gcc/testsuite/gcc.target/s390/20020926-1.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Make sure that LEGITIMIZE_ADDRESS is called to handle - negative displacements. */ - -/* { dg-do compile { target { s390-*-* } } } */ -/* { dg-options "-O2 -mesa" } */ - -int test (int *addr) -{ - return *(addr - 1); -} - -/* { dg-final { scan-assembler "-4096" } } */ -/* { dg-final { scan-assembler-not "ahi" } } */ - diff --git a/gcc/testsuite/gcc.target/s390/20140327-1.c b/gcc/testsuite/gcc.target/s390/20140327-1.c deleted file mode 100644 index 25c739137721..000000000000 --- a/gcc/testsuite/gcc.target/s390/20140327-1.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile { target { ! lp64 } } } */ -/* { dg-options "-O3 -mzarch" } */ - -void -foo () -{ - asm ("" ::: "%f4"); -} - -/* { dg-final { scan-assembler "ld" } } */ diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c index ebc024795872..d6f3ad9cf641 100644 --- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c +++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 -march=z13 -mzarch --save-temps" } */ +/* { dg-options "-O3 -march=z13 --save-temps" } */ #include <stddef.h> #include <limits.h> @@ -74,10 +74,7 @@ main () /* { dg-final { scan-assembler-not "\tcgr" } } */ /* { dg-final { scan-assembler-not "\txgr" } } */ /* { dg-final { scan-assembler-not "\tngr" } } */ -/* On 31 bit the long long variants use risbgn to merge the 32 bit - regs into a 64 bit reg. */ -/* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ +/* { dg-final { scan-assembler-not "\trisbg" } } */ /* Just one for the ret != 6 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ -/* { dg-final { scan-assembler-times "\tlochio\t" 6 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tlocghio\t" 6 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 6 } } */ diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c index 8bd1a764bc68..63eb8a683a5b 100644 --- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c +++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 -march=z13 -mzarch --save-temps" } */ +/* { dg-options "-O3 -march=z13 --save-temps" } */ #include <stddef.h> #include <limits.h> @@ -73,10 +73,7 @@ main () /* { dg-final { scan-assembler-not "\tcgr" } } */ /* { dg-final { scan-assembler-not "\txgr" } } */ /* { dg-final { scan-assembler-not "\tngr" } } */ -/* On 31 bit the long long variants use risbgn to merge the 32 bit - regs into a 64 bit reg. */ -/* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ +/* { dg-final { scan-assembler-not "\trisbg" } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ -/* { dg-final { scan-assembler-times "\tlochio\t" 6 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tlocghio\t" 6 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 6 */ diff --git a/gcc/testsuite/gcc.target/s390/asm-constant-1.c b/gcc/testsuite/gcc.target/s390/asm-constant-1.c index 980bea1cfab0..e76904eb3457 100644 --- a/gcc/testsuite/gcc.target/s390/asm-constant-1.c +++ b/gcc/testsuite/gcc.target/s390/asm-constant-1.c @@ -1,11 +1,9 @@ /* { dg-do compile } */ -/* { dg-final { scan-assembler {# 127 127 128 128 32767 32767 32768 32768 2147483647 2147483647 -2147483648 -2147483648} { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler {# 127 127 128 128 32767 32767 32768 32768 2147483647 2147483647 2147483648 2147483648 9223372036854775807 9223372036854775807 -9223372036854775808 -9223372036854775808} { target lp64 } } } */ +/* { dg-final { scan-assembler {# 127 127 128 128 32767 32767 32768 32768 2147483647 2147483647 2147483648 2147483648 9223372036854775807 9223372036854775807 -9223372036854775808 -9223372036854775808} } } */ void test (void) { -#ifdef __s390x__ __asm__ __volatile__ ("# %0 %c0 %1 %c1 %2 %c2 %3 %c3 %4 %c4 %5 %c5 %6 %c6 %7 %c7" :: "i" (0x7f), "i" (0x80), @@ -15,13 +13,4 @@ test (void) "i" (0x80000000L), "i" (0x7fffffffffffffffL), "i" (0x8000000000000000L)); -#else - __asm__ __volatile__ ("# %0 %c0 %1 %c1 %2 %c2 %3 %c3 %4 %c4 %5 %c5" :: - "i" (0x7f), - "i" (0x80), - "i" (0x7fff), - "i" (0x8000), - "i" (0x7fffffff), - "i" (0x80000000L)); -#endif } diff --git a/gcc/testsuite/gcc.target/s390/call-z10-pic-nodatarel.c b/gcc/testsuite/gcc.target/s390/call-z10-pic-nodatarel.c index 6df0c75584f4..0f0093f34fc8 100644 --- a/gcc/testsuite/gcc.target/s390/call-z10-pic-nodatarel.c +++ b/gcc/testsuite/gcc.target/s390/call-z10-pic-nodatarel.c @@ -1,18 +1,15 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=z10 -mzarch -fPIC -mno-pic-data-is-text-relative" } */ +/* { dg-options "-O3 -march=z10 -fPIC -mno-pic-data-is-text-relative" } */ #include "call.h" /* { dg-final { scan-assembler {brasl\t%r\d+,foo@PLT\n} } } */ -/* { dg-final { scan-assembler {lgrl\t%r2,foo@GOTENT\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {lrl\t%r2,foo@GOTENT\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {lgrl\t%r2,foo@GOTENT\n} } } */ /* { dg-final { scan-assembler {brasl\t%r\d+,foostatic@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r2,foostatic\n} } } */ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ -/* { dg-final { scan-assembler {lgrl\t%r2,fooweak@GOTENT\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {lrl\t%r2,fooweak@GOTENT\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {lgrl\t%r2,fooweak@GOTENT\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/call-z10-pic.c b/gcc/testsuite/gcc.target/s390/call-z10-pic.c index 30145d5b7608..4da626310b18 100644 --- a/gcc/testsuite/gcc.target/s390/call-z10-pic.c +++ b/gcc/testsuite/gcc.target/s390/call-z10-pic.c @@ -4,15 +4,12 @@ #include "call.h" /* { dg-final { scan-assembler {brasl\t%r\d+,foo@PLT\n} } } */ -/* { dg-final { scan-assembler {lgrl\t%r2,foo@GOTENT\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {lrl\t%r2,foo@GOTENT\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {lgrl\t%r2,foo@GOTENT\n} } } */ /* { dg-final { scan-assembler {brasl\t%r\d+,foostatic@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r2,foostatic\n} } } */ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ -/* { dg-final { scan-assembler {lgrl\t%r2,fooweak@GOTENT\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {lrl\t%r2,fooweak@GOTENT\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {lgrl\t%r2,fooweak@GOTENT\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/call-z10.c b/gcc/testsuite/gcc.target/s390/call-z10.c index d4eab4ff89fc..c261838d62a8 100644 --- a/gcc/testsuite/gcc.target/s390/call-z10.c +++ b/gcc/testsuite/gcc.target/s390/call-z10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=z10 -mzarch" } */ +/* { dg-options "-O3 -march=z10" } */ #include "call.h" @@ -12,5 +12,4 @@ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r2,fooweak\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/call-z9-pic-nodatarel.c b/gcc/testsuite/gcc.target/s390/call-z9-pic-nodatarel.c index fe515bf1903d..d36b760b9e2e 100644 --- a/gcc/testsuite/gcc.target/s390/call-z9-pic-nodatarel.c +++ b/gcc/testsuite/gcc.target/s390/call-z9-pic-nodatarel.c @@ -12,5 +12,4 @@ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r\d+,fooweak@GOTENT\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/call-z9-pic.c b/gcc/testsuite/gcc.target/s390/call-z9-pic.c index 43e1c2f7cb38..3bfd5a8199bb 100644 --- a/gcc/testsuite/gcc.target/s390/call-z9-pic.c +++ b/gcc/testsuite/gcc.target/s390/call-z9-pic.c @@ -12,5 +12,4 @@ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r\d+,fooweak@GOTENT\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/call-z9.c b/gcc/testsuite/gcc.target/s390/call-z9.c index b755f33498a3..f2b0f78fa41e 100644 --- a/gcc/testsuite/gcc.target/s390/call-z9.c +++ b/gcc/testsuite/gcc.target/s390/call-z9.c @@ -12,5 +12,4 @@ /* { dg-final { scan-assembler {brasl\t%r\d+,fooweak@PLT\n} } } */ /* { dg-final { scan-assembler {larl\t%r2,fooweak\n} } } */ -/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} { target lp64 } } } */ -/* { dg-final { scan-assembler {foos:\n\t.long\tfoo\n\t.long\tfoostatic\n\t.long\tfooweak\n} { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler {foos:\n\t.quad\tfoo\n\t.quad\tfoostatic\n\t.quad\tfooweak\n} } } */ diff --git a/gcc/testsuite/gcc.target/s390/dwarfregtable-1.c b/gcc/testsuite/gcc.target/s390/dwarfregtable-1.c deleted file mode 100644 index b12549874515..000000000000 --- a/gcc/testsuite/gcc.target/s390/dwarfregtable-1.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Make sure the dwarf reg size table doesn't change for 31 bit. */ - -/* { dg-do compile { target { ! lp64 } } } */ -/* { dg-options "-mesa" } */ - -#define DWARF_FRAME_REGISTERS 34 - -static unsigned char dwarf_reg_size_table[DWARF_FRAME_REGISTERS + 1]; -static unsigned char ref_reg_size_table[DWARF_FRAME_REGISTERS + 1] = - { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 0 }; - -int -main () -{ - __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); - if (__builtin_memcmp (ref_reg_size_table, - dwarf_reg_size_table, DWARF_FRAME_REGISTERS + 1) != 0) - __builtin_abort (); - return 0; -} diff --git a/gcc/testsuite/gcc.target/s390/dwarfregtable-2.c b/gcc/testsuite/gcc.target/s390/dwarfregtable-2.c deleted file mode 100644 index bc5a9f8e6d84..000000000000 --- a/gcc/testsuite/gcc.target/s390/dwarfregtable-2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Make sure the dwarf reg size table doesn't change for 31 bit zarch. */ - -/* { dg-do compile { target { ! lp64 } } } */ -/* { dg-options "-mzarch" } */ - -#define DWARF_FRAME_REGISTERS 34 - -static unsigned char dwarf_reg_size_table[DWARF_FRAME_REGISTERS + 1]; -static unsigned char ref_reg_size_table[DWARF_FRAME_REGISTERS + 1] = - { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 0 }; - -int -main () -{ - __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); - if (__builtin_memcmp (ref_reg_size_table, - dwarf_reg_size_table, DWARF_FRAME_REGISTERS + 1) != 0) - __builtin_abort (); - return 0; -} diff --git a/gcc/testsuite/gcc.target/s390/fcall-saved.c b/gcc/testsuite/gcc.target/s390/fcall-saved.c index a08155372f90..6a10bfabb519 100644 --- a/gcc/testsuite/gcc.target/s390/fcall-saved.c +++ b/gcc/testsuite/gcc.target/s390/fcall-saved.c @@ -1,11 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mzarch -fcall-saved-r4" } */ +/* { dg-options "-O3 -fcall-saved-r4" } */ void test(void) { asm volatile("nop" ::: "r4"); } -/* { dg-final { scan-assembler-times "\tstg\t" 1 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tlg\t" 1 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tst\t" 1 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tl\t" 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tstg\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tlg\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/fp2int1.c b/gcc/testsuite/gcc.target/s390/fp2int1.c deleted file mode 100644 index 4a90a8b91ded..000000000000 --- a/gcc/testsuite/gcc.target/s390/fp2int1.c +++ /dev/null @@ -1,95 +0,0 @@ -/* Test for the 32 bit fp to 64 bit int conversion routines. - - On S/390 32 bit we use our own implementations in order to be IEEE - complaint as we are with our machine instructions. These missed to - throw FE_INVALID exceptions in a bunch of cases. */ - -/* { dg-do run { target s390-*-* } } */ -/* { dg-options "-O3 -mesa" } */ -/* { dg-require-effective-target fenv_exceptions } */ - -#define _GNU_SOURCE -#include <stdlib.h> -#include <stdio.h> -#include <fenv.h> - -#define INFINITYf (__builtin_inff()) -#define INFINITY (__builtin_inf()) -#define INFINITYl (__builtin_infl()) -#define NANf (__builtin_nanf ("")) -#define NAN (__builtin_nan ("")) -#define NANl (__builtin_nanl ("")) - -#define TESTEXCEPT_FUNC(FUNC, TYPE_FROM, TYPE_TO) \ - TYPE_TO \ - __attribute__((noinline)) FUNC (TYPE_FROM a) \ - { \ - asm volatile ("" : : "f" (a)); \ - return (TYPE_TO)a; \ - } - -#define TESTEXCEPT(FUNC, EXCEPT, EXPECT, VALUE, TYPE_TO) \ - { \ - TYPE_TO b; \ - feclearexcept (FE_ALL_EXCEPT); \ - b = FUNC (VALUE); \ - if ((fetestexcept (EXCEPT) & (EXCEPT)) != EXPECT) \ - { \ - printf ("FAIL in line: %d\n", __LINE__); \ - abort (); \ - } \ - } - -#define TESTEXCEPT_FUNC_ALLFLOATS(FUNC, TYPE_TO) \ - TESTEXCEPT_FUNC (FUNC##_f, float, TYPE_TO); \ - TESTEXCEPT_FUNC (FUNC##_d, double, TYPE_TO); \ - TESTEXCEPT_FUNC (FUNC##_l, long double, TYPE_TO); \ - -#define TESTEXCEPT_ALLFLOATS(FUNC, EXCEPT, EXPECT, VALUE, TYPE_TO) \ - TESTEXCEPT (FUNC##_f, EXCEPT, EXPECT, VALUE##f, TYPE_TO); \ - TESTEXCEPT (FUNC##_d, EXCEPT, EXPECT, VALUE, TYPE_TO); \ - TESTEXCEPT (FUNC##_l, EXCEPT, EXPECT, VALUE##l, TYPE_TO); \ - -TESTEXCEPT_FUNC_ALLFLOATS (a, unsigned long long); -TESTEXCEPT_FUNC_ALLFLOATS (u, long long); - - -int -main () -{ - /* Prevent getting signals. */ - fedisableexcept (FE_INVALID); - - /* To unsigned long long */ - - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, INFINITY, unsigned long long); - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -INFINITY, unsigned long long); - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, NAN, unsigned long long); - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -NAN, unsigned long long); - - /* Negative values >-1.0 must not cause FE_INVALID. */ - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, 0, -0x0.ffffffp0, unsigned long long); - /* -1.0 instead must. */ - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -0x1.0p+0, unsigned long long); - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, 0, 0x1.0p+63, unsigned long long); - TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, 0x1.0p+64, unsigned long long); - - /* To signed long long */ - - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, INFINITY, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -INFINITY, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, NAN, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -NAN, long long); - - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, 0, -0x1.0p+63, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -0x1.1p+63, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, 0, 0x0.fffffp+63, long long); - TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, 0x1.0p+63, long long); - - /* If there are additional bits which would not make it into the - integer value no exception is supposed to occur. */ - TESTEXCEPT (u_l, FE_INVALID, 0, -0x1.000000000000000123p+63l, long long); - TESTEXCEPT (u_l, FE_INVALID, FE_INVALID, -0x1.000000000000000223p+63l, long long); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c b/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c index 0ee10841cac5..72b87d40b855 100644 --- a/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c +++ b/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c @@ -1,6 +1,6 @@ /* Test accesses to global array elements in PIC code. */ /* { dg-do compile } */ -/* { dg-options "-O1 -march=z10 -mzarch -fPIC" } */ +/* { dg-options "-O1 -march=z10 -fPIC" } */ extern char a[] __attribute__ ((aligned (2))); extern char *b; @@ -8,7 +8,6 @@ extern char *b; void c() { b = a + 4; - /* { dg-final { scan-assembler "(?n)\n\tlgrl\t%r\\d+,a@GOTENT\n" { target lp64 } } } */ - /* { dg-final { scan-assembler "(?n)\n\tlrl\t%r\\d+,a@GOTENT\n" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "(?n)\n\tlgrl\t%r\\d+,a@GOTENT\n" } } */ /* { dg-final { scan-assembler-not "(?n)\n\tlarl\t%r\\d+,a\[^@\]" } } */ } diff --git a/gcc/testsuite/gcc.target/s390/insv-1.c b/gcc/testsuite/gcc.target/s390/insv-1.c index 020b5d8e3c04..206646e04e75 100644 --- a/gcc/testsuite/gcc.target/s390/insv-1.c +++ b/gcc/testsuite/gcc.target/s390/insv-1.c @@ -109,10 +109,4 @@ foo4c (unsigned long a, unsigned long b) } /* The functions foo3, foo4, foo3b, foo4b no longer use risbg but rosbg instead. - - On 64 bit, four risbg go away and four new ones appear in other functions - { dg-final { scan-assembler-times "risbg" 6 { target { lp64 } } } } - - ... but not on 31 bit. - { dg-final { scan-assembler-times "risbg" 2 { target { ! lp64 } } } } -*/ + { dg-final { scan-assembler-times "risbg" 6 } } */ diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c index e1c7806ad96f..4afc22054295 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c @@ -3,10 +3,8 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT long double */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT _Decimal128 */ -/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT long double */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 } } SIGNBIT _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,4032} 1 } } ISFINITE long double */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } ISFINITE _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,48} 1 } } ISINF long double */ diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c index 5c9986d06006..cb5c788eef40 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c @@ -3,10 +3,8 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,48} 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/larl-1.c b/gcc/testsuite/gcc.target/s390/larl-1.c index e22975ba9601..2ec96ab6c028 100644 --- a/gcc/testsuite/gcc.target/s390/larl-1.c +++ b/gcc/testsuite/gcc.target/s390/larl-1.c @@ -1,14 +1,13 @@ /* Check if load-address-relative instructions are created */ -/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -march=z10 -mzarch -fno-section-anchors" } */ /* An explicitly misaligned symbol. This symbol is NOT aligned as mandated by our ABI. However, the back-end needs to handle that in order to make things like __attribute__((packed)) work. The symbol address is expected to be loaded from literal pool. */ -/* { dg-final { scan-assembler "lgrl\t%r2," { target { lp64 } } } } */ -/* { dg-final { scan-assembler "lrl\t%r2," { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "lgrl\t%r2," } } */ extern char align1 __attribute__((aligned(1))); /* { dg-final { scan-assembler "larl\t%r2,align2" } } */ diff --git a/gcc/testsuite/gcc.target/s390/leaf-profile.c b/gcc/testsuite/gcc.target/s390/leaf-profile.c index 604774007575..fbb2f1c37487 100644 --- a/gcc/testsuite/gcc.target/s390/leaf-profile.c +++ b/gcc/testsuite/gcc.target/s390/leaf-profile.c @@ -6,5 +6,4 @@ foo () { } /* Make sure no stack frame is generated. */ -/* { dg-final { scan-assembler-not "ahi" { target s390-*-* } } } */ /* { dg-final { scan-assembler-not "aghi" { target s390x-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/s390/load-relative-check.c b/gcc/testsuite/gcc.target/s390/load-relative-check.c index a55bc2442f17..7c85347b2d2a 100644 --- a/gcc/testsuite/gcc.target/s390/load-relative-check.c +++ b/gcc/testsuite/gcc.target/s390/load-relative-check.c @@ -1,14 +1,10 @@ /* Check if load-relative instructions are created */ -/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-do compile } */ /* { dg-options "-O2 -march=z10 -mzarch -fno-section-anchors" } */ -/* { dg-final { scan-assembler "lgfrl\t%r.?,b.4" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "lgfrl\t%r.?,s.12" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "lgrl\t%r.?,s" { target { lp64 } } } } */ - -/* { dg-final { scan-assembler "lrl\t%r.?,b.4" { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler "lrl\t%r.?,s.8" { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler "lrl\t%r.?,s" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "lgfrl\t%r.?,b.4" } } */ +/* { dg-final { scan-assembler "lgfrl\t%r.?,s.12" } } */ +/* { dg-final { scan-assembler "lgrl\t%r.?,s" } } */ int b[20]; diff --git a/gcc/testsuite/gcc.target/s390/load-thread-pointer-once-2.c b/gcc/testsuite/gcc.target/s390/load-thread-pointer-once-2.c index 36b1ed8800f1..e69acd959f80 100644 --- a/gcc/testsuite/gcc.target/s390/load-thread-pointer-once-2.c +++ b/gcc/testsuite/gcc.target/s390/load-thread-pointer-once-2.c @@ -10,5 +10,4 @@ void a(void) c(b); } -/* { dg-final { scan-assembler-times {\n\tear\t} 2 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times {\n\tear\t} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\n\tear\t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/s390/load-thread-pointer-once.c b/gcc/testsuite/gcc.target/s390/load-thread-pointer-once.c index 21a5bfaa7321..b127b6356c0f 100644 --- a/gcc/testsuite/gcc.target/s390/load-thread-pointer-once.c +++ b/gcc/testsuite/gcc.target/s390/load-thread-pointer-once.c @@ -8,5 +8,4 @@ void *bar() return (foo = __builtin_thread_pointer()); } -/* { dg-final { scan-assembler-times {\n\tear\t} 2 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times {\n\tear\t} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\n\tear\t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/s390/loc-1.c b/gcc/testsuite/gcc.target/s390/loc-1.c index 26dbd9cecb38..cfe0a122f55b 100644 --- a/gcc/testsuite/gcc.target/s390/loc-1.c +++ b/gcc/testsuite/gcc.target/s390/loc-1.c @@ -9,8 +9,7 @@ unsigned long loc_r (unsigned long rc, unsigned long cond, unsigned long val) rc = val; return rc; } -/* { dg-final { scan-assembler "\tlocgrne\t%r2,%r4" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "\tlocrne\t%r2,%r4" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "\tlocgrne\t%r2,%r4" } } */ long loc_hi (long rc, long cond) { @@ -18,5 +17,4 @@ long loc_hi (long rc, long cond) rc = (long)-1; return rc; } -/* { dg-final { scan-assembler "\tlocghine\t%r2,-1" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "\tlochine\t%r2,-1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "\tlocghine\t%r2,-1" } } */ diff --git a/gcc/testsuite/gcc.target/s390/md/andc-splitter-2.c b/gcc/testsuite/gcc.target/s390/md/andc-splitter-2.c index 7d098d8d987e..96e15452f6d1 100644 --- a/gcc/testsuite/gcc.target/s390/md/andc-splitter-2.c +++ b/gcc/testsuite/gcc.target/s390/md/andc-splitter-2.c @@ -16,25 +16,25 @@ __attribute__ ((noinline)) unsigned int andc_vv(unsigned int a, unsigned int b) { return ~b & a; } -/* { dg-final { scan-assembler ":18:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */ +/* { dg-final { scan-assembler ":18:.\* \{\\*andsi3\}" } } */ /* { dg-final { scan-assembler ":18:.\* \{\\*xorsi3\}" } } */ __attribute__ ((noinline)) unsigned int andc_pv(unsigned int *a, unsigned int b) { return ~b & *a; } -/* { dg-final { scan-assembler ":24:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */ +/* { dg-final { scan-assembler ":24:.\* \{\\*andsi3\}" } } */ /* { dg-final { scan-assembler ":24:.\* \{\\*xorsi3\}" } } */ __attribute__ ((noinline)) unsigned int andc_vp(unsigned int a, unsigned int *b) { return ~*b & a; } -/* { dg-final { scan-assembler ":30:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */ +/* { dg-final { scan-assembler ":30:.\* \{\\*andsi3\}" } } */ /* { dg-final { scan-assembler ":30:.\* \{\\*xorsi3\}" } } */ __attribute__ ((noinline)) unsigned int andc_pp(unsigned int *a, unsigned int *b) { return ~*b & *a; } -/* { dg-final { scan-assembler ":36:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */ +/* { dg-final { scan-assembler ":36:.\* \{\\*andsi3\}" } } */ /* { dg-final { scan-assembler ":36:.\* \{\\*xorsi3\}" } } */ /* { dg-final { scan-assembler-times "\tng\?r\?k\?\t" 4 } } */ diff --git a/gcc/testsuite/gcc.target/s390/mnop-mcount-m31-mzarch.c b/gcc/testsuite/gcc.target/s390/mnop-mcount-m31-mzarch.c deleted file mode 100644 index 874ceb96fe8a..000000000000 --- a/gcc/testsuite/gcc.target/s390/mnop-mcount-m31-mzarch.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-m31 -mzarch -pg -mnop-mcount" } */ - -void -profileme (void) -{ - /* { dg-final { scan-assembler "NOPs for -mnop-mcount \\(7 halfwords\\)\n.*brcl\t0,0\n.*brcl\t0,0\n.*bcr\t0,0" } } */ -} diff --git a/gcc/testsuite/gcc.target/s390/mrecord-mcount.c b/gcc/testsuite/gcc.target/s390/mrecord-mcount.c index 54ced9f7a11a..d8a23ffdca43 100644 --- a/gcc/testsuite/gcc.target/s390/mrecord-mcount.c +++ b/gcc/testsuite/gcc.target/s390/mrecord-mcount.c @@ -5,7 +5,6 @@ void profileme (void) { /* { dg-final { scan-assembler ".section __mcount_loc, \"a\",@progbits" } } */ - /* { dg-final { scan-assembler ".long 1b" { target { ! lp64 } } } } */ - /* { dg-final { scan-assembler ".quad 1b" { target { lp64 } } } } */ + /* { dg-final { scan-assembler ".quad 1b" } } */ /* { dg-final { scan-assembler ".previous" } } */ } diff --git a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c index e8b1938dab7e..20205bdabbdc 100644 --- a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c +++ b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c @@ -50,10 +50,7 @@ main () /* { dg-final { scan-assembler-not "\tcgr" } } */ /* { dg-final { scan-assembler-not "\txgr" } } */ /* { dg-final { scan-assembler-not "\tngr" } } */ -/* On 31 bit the long long variants use risbgn to merge the 32 bit - regs into a 64 bit reg. */ -/* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ +/* { dg-final { scan-assembler-not "\trisbg" } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ -/* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 3 } } */ diff --git a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c index 01328e1d286a..6c0e6fcfab06 100644 --- a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c +++ b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c @@ -52,8 +52,7 @@ main () /* { dg-final { scan-assembler-not "\tngr" } } */ /* On 31 bit the long long variants use risbgn to merge the 32 bit regs into a 64 bit reg. */ -/* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ +/* { dg-final { scan-assembler-not "\trisbg" } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ -/* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 3 } } */ diff --git a/gcc/testsuite/gcc.target/s390/not.c b/gcc/testsuite/gcc.target/s390/not.c index dae95f7d8a06..6a61312ba654 100644 --- a/gcc/testsuite/gcc.target/s390/not.c +++ b/gcc/testsuite/gcc.target/s390/not.c @@ -7,5 +7,4 @@ foo (unsigned long a) return ~a; } -/* { dg-final { scan-assembler-times "\tnngrk\t" 1 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times "\tnnrk\t" 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tnngrk\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/pr102222.c b/gcc/testsuite/gcc.target/s390/pr102222.c deleted file mode 100644 index 47d075e47fcc..000000000000 --- a/gcc/testsuite/gcc.target/s390/pr102222.c +++ /dev/null @@ -1,16 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -m31 -mesa" } */ - -struct squashfs_reg_inode_header_1 read_inode_inode; - -int read_inode_val; - -struct squashfs_reg_inode_header_1 -{ - int file_size:32; -} __attribute__((packed)) read_inode (); - -void foo (void) -{ - read_inode_inode.file_size = read_inode_val; -} diff --git a/gcc/testsuite/gcc.target/s390/pr106355-2.c b/gcc/testsuite/gcc.target/s390/pr106355-2.c deleted file mode 100644 index ddbdba5d278b..000000000000 --- a/gcc/testsuite/gcc.target/s390/pr106355-2.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile { target { s390-*-* } } } */ -/* { dg-options "-foptimize-sibling-calls -mzarch" } */ -/* { dg-final { scan-assembler {brasl\t%r\d+,bar} } } */ - -/* This tests function s390_call_saved_register_used where - GET_CODE (parm_rtx) == PARALLEL holds. */ - -#include "pr106355.h" diff --git a/gcc/testsuite/gcc.target/s390/pr106355-3.c b/gcc/testsuite/gcc.target/s390/pr106355-3.c deleted file mode 100644 index 39daea44fc4a..000000000000 --- a/gcc/testsuite/gcc.target/s390/pr106355-3.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile { target { s390-*-* } } } */ -/* { dg-options "-foptimize-sibling-calls -mesa" } */ -/* { dg-final { scan-assembler {brasl\t%r\d+,bar} } } */ - -/* This tests function s390_call_saved_register_used where - REG_P (parm_rtx) and nregs == 2 holds. */ - -#include "pr106355.h" diff --git a/gcc/testsuite/gcc.target/s390/pr119873-5.c b/gcc/testsuite/gcc.target/s390/pr119873-5.c deleted file mode 100644 index b5a7950d62b4..000000000000 --- a/gcc/testsuite/gcc.target/s390/pr119873-5.c +++ /dev/null @@ -1,11 +0,0 @@ -/* PR target/119873 */ -/* { dg-do compile } */ -/* { dg-options "-O2 -m31 -mzarch" } */ - -extern void foo (int x, int y, int z, long long w, int v); - -void -bar (int x, int y, int z, long long w, int v) -{ - [[gnu::musttail]] return foo (x, y, z, w, v); -} diff --git a/gcc/testsuite/gcc.target/s390/pr42224.c b/gcc/testsuite/gcc.target/s390/pr42224.c index 67146d20fb9b..c2ebc1329565 100644 --- a/gcc/testsuite/gcc.target/s390/pr42224.c +++ b/gcc/testsuite/gcc.target/s390/pr42224.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O0 -Wno-implicit-function-declaration" } */ +#ifdef __tpf__ + typedef char* __char_ptr32 __attribute__ (( mode (SI) )); typedef __char_ptr32 *__char_ptr_char_ptr32 __attribute__ ((mode (SI))); @@ -33,3 +35,4 @@ to_ptr32_ptr32 (char **ptr64) } +#endif diff --git a/gcc/testsuite/gcc.target/s390/pr61078.c b/gcc/testsuite/gcc.target/s390/pr61078.c deleted file mode 100644 index 40f6ad7df098..000000000000 --- a/gcc/testsuite/gcc.target/s390/pr61078.c +++ /dev/null @@ -1,26 +0,0 @@ -/* This testcase is extracted from s390_emit_prologue. The negation - of a 64bit value got split incorrectly on 31 bit. */ - -/* { dg-do run { target { ! lp64 } } } */ -/* { dg-options "-O2 -mesa" } */ - -extern void abort (void); - -long long frame_size = 42; - -int __attribute__((noinline)) -foo (int a __attribute__((unused)), long long b) -{ - return (int)b; -} - -int -main () -{ - if (frame_size > 0) - { - if (foo (0, -frame_size) != -42) - abort (); - } - return 0; -} diff --git a/gcc/testsuite/gcc.target/s390/preserve-args-1.c b/gcc/testsuite/gcc.target/s390/preserve-args-1.c index 24dcf547432a..c3c0229f58ae 100644 --- a/gcc/testsuite/gcc.target/s390/preserve-args-1.c +++ b/gcc/testsuite/gcc.target/s390/preserve-args-1.c @@ -10,8 +10,7 @@ foo (int a, int b, int c, double d, double e) return a + c + (int)d + (int)e; } -/* { dg-final { scan-assembler "stmg\t%r2,%r4,\[0-9\]*\\(%r15\\)" { target lp64 } } } */ -/* { dg-final { scan-assembler "stm\t%r2,%r4,\[0-9\]*\\(%r15\\)" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "stmg\t%r2,%r4,\[0-9\]*\\(%r15\\)" } } */ /* { dg-final { scan-assembler "std\t%f0,\[0-9\]*\\(%r15\\)" } } */ /* { dg-final { scan-assembler "std\t%f2,\[0-9\]*\\(%r15\\)" } } */ diff --git a/gcc/testsuite/gcc.target/s390/preserve-args-3.c b/gcc/testsuite/gcc.target/s390/preserve-args-3.c index f4b135ab8e66..53a73195c000 100644 --- a/gcc/testsuite/gcc.target/s390/preserve-args-3.c +++ b/gcc/testsuite/gcc.target/s390/preserve-args-3.c @@ -12,8 +12,7 @@ foo (int a, int, int c, double d, ...) return a + c + va_arg(argp, int) + va_arg(argp, int) + (int)va_arg(argp, double); } -/* { dg-final { scan-assembler "stmg\t%r2,%r15,\[0-9\]*\\(%r15\\)" { target lp64 } } } */ -/* { dg-final { scan-assembler "stm\t%r2,%r15,\[0-9\]*\\(%r15\\)" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "stmg\t%r2,%r15,\[0-9\]*\\(%r15\\)" } } */ /* { dg-final { scan-assembler "std\t%f0,\[0-9\]*\\(%r15\\)" } } */ /* { dg-final { scan-assembler "std\t%f2,\[0-9\]*\\(%r15\\)" } } */ diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c index 1cac15820c06..bebc796d009d 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c @@ -25,8 +25,7 @@ i32 f1 (i32 v_foo) // ...and again with i64. i64 f2 (i64 v_foo) { - /* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r2,64-1,128\\\+63,53\\\+1" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f2:\n\trisbg\t%r3,%r3,64-1,128\\\+63,53\\\+1\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r2,64-1,128\\\+63,53\\\+1" } } */ i64 v_shr = ((ui64)v_foo) >> 10; i64 v_and = v_shr & 1; return v_and; @@ -44,8 +43,7 @@ i32 f3 (i32 v_foo) // ...and again with i64. i64 f4 (i64 v_foo) { - /* { dg-final { scan-assembler "f4:\n\trisbg\t%r2,%r2,60,128\\\+61,64-22" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f4:\n\trisbg\t%r3,%r3,60,128\\\+61,64-22\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f4:\n\trisbg\t%r2,%r2,60,128\\\+61,64-22" } } */ i64 v_shr = ((ui64)v_foo) >> 22; i64 v_and = v_shr & 12; return v_and; @@ -64,8 +62,7 @@ i32 f5 (i32 v_foo) // ...and again with i64. i64 f6 (i64 v_foo) { - /* { dg-final { scan-assembler "f6:\n\trisbg\t%r2,%r2,2,128\\\+60,64-2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f6:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r2,%r3,2,128\\\+60,64-2" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f6:\n\trisbg\t%r2,%r2,2,128\\\+60,64-2" } } */ i64 v_shr = ((ui64)v_foo) >> 2; i64 v_and = v_shr & -8; return v_and; @@ -78,8 +75,7 @@ i32 f7 (i32 v_foo) /* Should be { dg-final { scan-assembler "f7:\n\tsrl\t%r2,2\n\tnill\t%r2,65529" { xfail { lp64 } } } } but because a zeroextend is merged into the pattern it is actually - { dg-final { scan-assembler "f7:\n\tsrl\t%r2,2\n\tlgfi\t%r1,1073741817\n\tngr\t%r2,%r1" { target { lp64 } } } } - { dg-final { scan-assembler "f7:\n\tsrl\t%r2,2\n\tnill\t%r2,65529" { target { ! lp64 } } } } */ + { dg-final { scan-assembler "f7:\n\tsrl\t%r2,2\n\tlgfi\t%r1,1073741817\n\tngr\t%r2,%r1" } } */ i32 v_shr = ((ui32)v_foo) >> 2; i32 v_and = v_shr & -7; return v_and; @@ -88,8 +84,7 @@ i32 f7 (i32 v_foo) // ...and again with i64. i64 f8 (i64 v_foo) { - /* { dg-final { scan-assembler "f8:\n\tsrlg\t%r2,%r2,2\n\tnill\t%r2,65529" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f8:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tsrlg\t%r2,%r3,2\n\tnill\t%r2,65529" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f8:\n\tsrlg\t%r2,%r2,2\n\tnill\t%r2,65529" } } */ i64 v_shr = ((ui64)v_foo) >> 2; i64 v_and = v_shr & -7; return v_and; @@ -108,8 +103,7 @@ i32 f9 (i32 v_foo) // ...and again with i64. i64 f10 (i64 v_foo) { - /* { dg-final { scan-assembler "f10:\n\trisbg\t%r2,%r2,56,128\\\+61,2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f10:\n\trisbg\t%r3,%r3,56,128\\\+61,2\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f10:\n\trisbg\t%r2,%r2,56,128\\\+61,2" } } */ i64 v_shr = v_foo << 2; i64 v_and = v_shr & 255; return v_and; @@ -128,8 +122,7 @@ i32 f11 (i32 v_foo) // ...and again with i64. i64 f12 (i64 v_foo) { - /* { dg-final { scan-assembler "f12:\n\tsllg\t%r2,%r2,2\n\tnill\t%r2,65295" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f12:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tsllg\t%r2,%r3,2\n\tnill\t%r2,65295" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f12:\n\tsllg\t%r2,%r2,2\n\tnill\t%r2,65295" } } */ i64 v_shr = v_foo << 2; i64 v_and = v_shr & -241; return v_and; @@ -140,8 +133,7 @@ i64 f12 (i64 v_foo) // shl are not used. i32 f13 (i32 v_foo) { - /* { dg-final { scan-assembler "f13:\n\trisbg\t%r2,%r2,56,128\\\+60,32\\\+14" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f13:\n\trll\t%r2,%r2,14\n\tnilf\t%r2,248" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f13:\n\trisbg\t%r2,%r2,56,128\\\+60,32\\\+14" } } */ i32 v_parta = v_foo << 14; i32 v_partb = ((ui32)v_foo) >> 18; i32 v_rotl = v_parta | v_partb; @@ -152,8 +144,7 @@ i32 f13 (i32 v_foo) // ...and again with i64. i64 f14 (i64 v_foo) { - /* { dg-final { scan-assembler "f14:\n\trisbg\t%r2,%r2,56,128\\\+60,14" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f14:\n\trisbg\t%r3,%r2,56,128\\\+60,46\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f14:\n\trisbg\t%r2,%r2,56,128\\\+60,14" } } */ i64 v_parta = v_foo << 14; i64 v_partb = ((ui64)v_foo) >> 50; i64 v_rotl = v_parta | v_partb; @@ -164,8 +155,7 @@ i64 f14 (i64 v_foo) // Try a case in which only the bits from the shl are used. i32 f15 (i32 v_foo) { - /* { dg-final { scan-assembler "f15:\n\trisbg\t%r2,%r2,47,128\\\+49,14" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f15:\n\trll\t%r2,%r2,14\n\tnilf\t%r2,114688" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f15:\n\trisbg\t%r2,%r2,47,128\\\+49,14" } } */ i32 v_parta = v_foo << 14; i32 v_partb = ((ui32)v_foo) >> 18; i32 v_rotl = v_parta | v_partb; @@ -176,8 +166,7 @@ i32 f15 (i32 v_foo) // ...and again with i64. i64 f16 (i64 v_foo) { - /* { dg-final { scan-assembler "f16:\n\trisbg\t%r2,%r2,47,128\\\+49,14" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f16:\n\trisbg\t%r3,%r3,47,128\\\+49,14\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f16:\n\trisbg\t%r2,%r2,47,128\\\+49,14" } } */ i64 v_parta = v_foo << 14; i64 v_partb = ((ui64)v_foo) >> 50; i64 v_rotl = v_parta | v_partb; @@ -192,8 +181,7 @@ i32 f17 (i32 v_foo) /* Should be { dg-final { scan-assembler "f17:\n\trll\t%r2,%r2,4\n\tnilf\t%r2,126" { xfail { lp64 } } } } but because a zeroextend is merged into the pattern it is actually - { dg-final { scan-assembler "f17:\n\trll\t%r2,%r2,4\n\trisbg\t%r2,%r2,57,128\\\+62,0" { target { lp64 } } } } - { dg-final { scan-assembler "f17:\n\trll\t%r2,%r2,4\n\tnilf\t%r2,126" { target { ! lp64 } } } } */ + { dg-final { scan-assembler "f17:\n\trll\t%r2,%r2,4\n\trisbg\t%r2,%r2,57,128\\\+62,0" } } */ i32 v_parta = v_foo << 4; i32 v_partb = ((ui32)v_foo) >> 28; i32 v_rotl = v_parta | v_partb; @@ -204,8 +192,7 @@ i32 f17 (i32 v_foo) // ...and for i64, where RISBG should do the rotate too. i64 f18 (i64 v_foo) { - /* { dg-final { scan-assembler "f18:\n\trisbg\t%r2,%r2,57,128\\\+62,4" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f18:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tlhi\t%r2,0\n\trisbg\t%r3,%r3,57,128\\\+62,4" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f18:\n\trisbg\t%r2,%r2,57,128\\\+62,4" } } */ i64 v_parta = v_foo << 4; i64 v_partb = ((ui64)v_foo) >> 60; i64 v_rotl = v_parta | v_partb; @@ -217,8 +204,7 @@ i64 f18 (i64 v_foo) // This needs a separate shift and mask on 31 bit. i32 f19 (i32 v_foo) { - /* { dg-final { scan-assembler "f19:\n\trisbg\t%r2,%r2,59,128\\+62,64-28" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f19:\n\tsra\t%r2,28\n\tnilf\t%r2,30" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f19:\n\trisbg\t%r2,%r2,59,128\\+62,64-28" } } */ i32 v_shr = v_foo >> 28; i32 v_and = v_shr & 30; return v_and; @@ -227,8 +213,7 @@ i32 f19 (i32 v_foo) // ...and again with i64. In this case RISBG is the best way of doing the AND. i64 f20 (i64 v_foo) { - /* { dg-final { scan-assembler "f20:\n\tsrag\t%r2,%r2,60\n\trisbg\t%r2,%r2,59,128\\\+62,0" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f20:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tlhi\t%r2,0\n\tsrag\t%r3,%r3,60\n\tnilf\t%r3,30" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f20:\n\tsrag\t%r2,%r2,60\n\trisbg\t%r2,%r2,59,128\\\+62,0" } } */ i64 v_shr = v_foo >> 60; i64 v_and = v_shr & 30; return v_and; @@ -248,8 +233,7 @@ i32 f21 (i32 v_foo) // ...and again with i64. i64 f22 (i64 v_foo) { - /* { dg-final { scan-assembler "f22:\n\trisbg\t%r2,%r2,60,128\\\+62,64-60" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f22:\n\trisbg\t%r3,%r2,60,128\\\+62,64-28\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f22:\n\trisbg\t%r2,%r2,60,128\\\+62,64-60" } } */ i64 v_shr = v_foo >> 60; i64 v_and = v_shr & 14; return v_and; @@ -259,8 +243,7 @@ i64 f22 (i64 v_foo) // natural zero extension. i64 f23 (i64 v_foo) { - /* { dg-final { scan-assembler "f23:\n\trisbg\t%r2,%r2,64-8,128\\\+63,54\\\+8" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f23:\n\trisbg\t%r3,%r3,64-8,128\\\+63,54\\\+8\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f23:\n\trisbg\t%r2,%r2,64-8,128\\\+63,54\\\+8" } } */ i64 v_shr = ((ui64)v_foo) >> 2; i64 v_and = v_shr & 255; return v_and; @@ -281,8 +264,7 @@ i32 f24 (i32 v_foo) // ...and again with i64, where a single RISBG is enough. i64 f25 (i64 v_foo) { - /* { dg-final { scan-assembler "f25:\n\trisbg\t%r2,%r2,57,128\\\+59,3" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f25:\n\trisbg\t%r3,%r3,57,128\\\+59,3\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f25:\n\trisbg\t%r2,%r2,57,128\\\+59,3" } } */ i64 v_and = v_foo & 14; i64 v_parta = v_and << 3; i64 v_partb = ((ui64)v_and) >> 61; @@ -305,8 +287,7 @@ i32 f26 (i32 v_foo) // ...and again with i64, where a single RISBG is OK. i64 f27 (i64 v_foo) { - /* { dg-final { scan-assembler "f27:\n\trisbg\t%r2,%r2,55,128\\\+52,5" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f27:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r2,%r3,55,128\\\+52,5" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f27:\n\trisbg\t%r2,%r2,55,128\\\+52,5" } } */ i64 v_and = v_foo & -49; i64 v_parta = v_and << 5; i64 v_partb = ((ui64)v_and) >> 59; @@ -326,8 +307,7 @@ i32 f28 (i32 v_foo) // ...and again with i64. i64 f29 (i64 v_foo) { - /* { dg-final { scan-assembler "f29:\n\trisbg\t%r2,%r2,0,128\\\+13,49" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f29:\n\trisbg\t%r\[23\],%r3,0,128\\\+13,49\n\tlr\t%r\[23\],%r\[32\]\n\tsrlg\t%r2,%r2" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f29:\n\trisbg\t%r2,%r2,0,128\\\+13,49" } } */ i64 v_and = v_foo & 32766; i64 v_shl = v_and << 49; return v_shl; @@ -345,8 +325,7 @@ i32 f30 (i32 v_foo) // ...and again with i64. i64 f31 (i64 v_foo) { - /* { dg-final { scan-assembler "f31:\n\trisbg\t%r2,%r2,0,128\\\+12,50" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f31:\n\trisbg\t%r\[23\],%r3,0,128\\\+12,50\n\tlr\t%r\[23\],%r\[32\]\n\tsrlg\t%r2,%r2" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f31:\n\trisbg\t%r2,%r2,0,128\\\+12,50" } } */ i64 v_and = v_foo & 32766; i64 v_shl = v_and << 50; return v_shl; @@ -365,8 +344,7 @@ i32 f32 (i32 v_foo) // ...and again with i64. i64 f33 (i64 v_foo) { - /* { dg-final { scan-assembler "f33:\n\tsllg\t%r2,%r2,10\n\tnill\t%r2,58368" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f33:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tsllg\t%r2,%r3,10\n\tnill\t%r2,58368" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f33:\n\tsllg\t%r2,%r2,10\n\tnill\t%r2,58368" } } */ i64 v_and = v_foo & -7; i64 v_shl = v_and << 10; return v_shl; @@ -384,8 +362,7 @@ i32 f34 (i32 v_foo) // ...and again with i64. i64 f35 (i64 v_foo) { - /* { dg-final { scan-assembler "f35:\n\trisbg\t%r2,%r2,64-7,128\\\+63,48\\\+7" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f35:\n\trisbg\t%r3,%r3,64-7,128\\\+63,48\\\+7\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f35:\n\trisbg\t%r2,%r2,64-7,128\\\+63,48\\\+7" } } */ i64 v_and = v_foo & 65535; i64 v_shl = ((ui64)v_and) >> 9; return v_shl; @@ -395,8 +372,7 @@ i64 f35 (i64 v_foo) // We can't use RISBG for the shift in that case. i32 f36 (i32 v_foo) { - /* { dg-final { scan-assembler "f36:\n\tsrl\t%r2,1\n\tlgfi\t%r1,2147483635\n\tngr\t%r2,%r1" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f36:\n\tsrl\t%r2,1\n\tnilf\t%r2,2147483635" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f36:\n\tsrl\t%r2,1\n\tlgfi\t%r1,2147483635\n\tngr\t%r2,%r1" } } */ i32 v_and = v_foo & -25; i32 v_shl = ((ui32)v_and) >> 1; return v_shl; @@ -405,8 +381,7 @@ i32 f36 (i32 v_foo) // ...and again with i64. i64 f37 (i64 v_foo) { - /* { dg-final { scan-assembler "f37:\n\(\t.*\n\)*\tsrlg\t%r2,%r2,1\n\tng\t%r2," { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f37:\n\(\t.*\n\)*\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tsrlg\t%r2,%r3,1\n\tng\t%r2," { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f37:\n\(\t.*\n\)*\tsrlg\t%r2,%r2,1\n\tng\t%r2," } } */ i64 v_and = v_foo & -25; i64 v_shl = ((ui64)v_and) >> 1; return v_shl; @@ -416,8 +391,7 @@ i64 f37 (i64 v_foo) // use RISBG there. i64 f38 (i64 v_foo) { - /* { dg-final { scan-assembler "f38:\n\tsrag\t%r2,%r2,32\n\tsllg\t%r2,%r2,5" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f38:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tsrag\t%r2,%r3,32\n\tsllg\t%r2,%r2,5" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f38:\n\tsrag\t%r2,%r2,32\n\tsllg\t%r2,%r2,5" } } */ i64 v_ashr = v_foo >> 32; i64 v_shl = v_ashr << 5; return v_shl; @@ -426,8 +400,7 @@ i64 f38 (i64 v_foo) // Try a similar thing in which no shifted sign bits are kept. i64 f39 (i64 v_foo, i64 *v_dest) { - /* { dg-final { scan-assembler "f39:\n\tsrag\t%r2,%r2,35\n\(\t.*\n\)*\trisbg\t%r2,%r2,33,128\\\+61,2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f39:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tlhi\t%r2,0\n\tsrag\t%r3,%r3,35\n\(\t.*\n\)*\trisbg\t%r3,%r3,33,128\\\+61,2" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f39:\n\tsrag\t%r2,%r2,35\n\(\t.*\n\)*\trisbg\t%r2,%r2,33,128\\\+61,2" } } */ i64 v_ashr = v_foo >> 35; *v_dest = v_ashr; i64 v_shl = v_ashr << 2; @@ -438,8 +411,7 @@ i64 f39 (i64 v_foo, i64 *v_dest) // ...and again with the next highest shift value, where one sign bit is kept. i64 f40 (i64 v_foo, i64 *v_dest) { - /* { dg-final { scan-assembler "f40:\n\tsrag\t%r2,%r2,36\n\(\t.*\n\)*\trisbg\t%r2,%r2,33,128\\\+61,2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f40:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\tlhi\t%r2,0\n\tsrag\t%r3,%r3,36\n\(\t.*\n\)*\trisbg\t%r3,%r3,33,128\\\+61,2" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f40:\n\tsrag\t%r2,%r2,36\n\(\t.*\n\)*\trisbg\t%r2,%r2,33,128\\\+61,2" } } */ i64 v_ashr = v_foo >> 36; *v_dest = v_ashr; i64 v_shl = v_ashr << 2; @@ -450,8 +422,7 @@ i64 f40 (i64 v_foo, i64 *v_dest) // Check a case where the result is zero-extended. i64 f41 (i32 v_a) { - /* { dg-final { scan-assembler "f41:\n\trisbg\t%r2,%r2,64-28,128\\\+63,34\\\+28" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f41:\n\trisbg\t%r3,%r2,64-28,128\\\+63,34\\\+28\n\tlhi\t%r2,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f41:\n\trisbg\t%r2,%r2,64-28,128\\\+63,34\\\+28" } } */ i32 v_shl = v_a << 2; i32 v_shr = ((ui32)v_shl) >> 4; i64 v_ext = (ui64)v_shr; @@ -464,8 +435,7 @@ i64 f41 (i32 v_a) typedef struct { ui64 pad : 63; ui8 a : 1; } t42; i64 f42 (t42 v_x) { - /* { dg-final { scan-assembler "f42:\n\tsllg\t%r2,%r2,63\n\tsrag\t%r2,%r2,63\n\tllgcr\t%r2,%r2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f42:\n\tsllg\t%r3,%r3,63\n\tlhi\t%r2,0\n\tsrag\t%r3,%r3,63\n\tllcr\t%r3,%r3" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f42:\n\tsllg\t%r2,%r2,63\n\tsrag\t%r2,%r2,63\n\tllgcr\t%r2,%r2" } } */ ui8 a = v_x.a << 7; i8 ext = ((i8)a) >> 7; i64 ext2 = (ui64)(ui8)ext; @@ -475,8 +445,7 @@ i64 f42 (t42 v_x) // Check that we get the case where a 64-bit shift is used by a 32-bit and. i32 f43 (i64 v_x) { - /* { dg-final { scan-assembler "f43:\n\trisbg\t%r2,%r2,32,128\\+61,32\\+20\n\tlgfr\t%r2,%r2" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f43:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r2,%r3,32,128\\\+61,64-12" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f43:\n\trisbg\t%r2,%r2,32,128\\+61,32\\+20\n\tlgfr\t%r2,%r2" } } */ i64 v_shr3 = ((ui64)v_x) >> 12; i32 v_shr3_tr = (ui32)v_shr3; i32 v_conv = v_shr3_tr & -4; @@ -486,8 +455,7 @@ i32 f43 (i64 v_x) // Check that we don't get the case where the 32-bit and mask is not contiguous i32 f44 (i64 v_x) { - /* { dg-final { scan-assembler "f44:\n\tsrlg\t%r2,%r2,12" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f44:\n\tsrlg\t%r2,%r3,12\n\tnilf\t%r2,10" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f44:\n\tsrlg\t%r2,%r2,12" } } */ i64 v_shr4 = ((ui64)v_x) >> 12; i32 v_conv = (ui32)v_shr4; i32 v_and = v_conv & 10; diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c index ca80602a83ff..b049456157cb 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c @@ -23,8 +23,7 @@ i32 f1 (i32 v_a, i32 v_b) // ...and again with i64. i64 f2 (i64 v_a, i64 v_b) { - /* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r3,60,62,0" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f2:\n\trisbg\t%r3,%r2,0,0\\\+32-1,64-0-32\n\(\t.*\n\)*\trisbg\t%r\[23\],%r5,60,62,0" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r3,60,62,0" } } */ i64 v_anda = v_a & -15; i64 v_andb = v_b & 14; i64 v_or = v_anda | v_andb; @@ -45,8 +44,7 @@ i32 f3 (i32 v_a, i32 v_b) // ...and again with i64. i64 f4 (i64 v_a, i64 v_b) { - /* { dg-final { scan-assembler "f4:\n\trisbg\t%r2,%r3,64-4,63,\\(64-64\\)\\+4\\+52" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f4:\n\(\t.*\n\)*\trisbg\t%r5,%r5,64-4,128\\+63,\\(64-64\\)\\+52\\+4" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f4:\n\trisbg\t%r2,%r3,64-4,63,\\(64-64\\)\\+4\\+52" } } */ i64 v_anda = v_a & -16; i64 v_shr = ((ui64)v_b) >> 8; i64 v_andb = v_shr & 15; @@ -67,8 +65,7 @@ i32 f5 (i32 v_a, i32 v_b) // ...and again with i64. i64 f6 (i64 v_a, i64 v_b) { - /* { dg-final { scan-assembler "f6:\n\trisbg\t%r2,%r3,0,64-10-1,10" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f6:\n\trisbg\t%r5,%r4,0,0\\\+32-1,64-0-32\n\(\t.*\n\)*\trisbg\t%r\[23\],%r5,0,64-10-1,10" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f6:\n\trisbg\t%r2,%r3,0,64-10-1,10" } } */ i64 v_anda = v_a & 1023; i64 v_shlb = v_b << 10; i64 v_or = v_anda | v_shlb; @@ -88,8 +85,7 @@ i32 f7 (i32 v_a, i32 v_b) // ...and again with i64. i64 f8 (i64 v_a, i64 v_b) { - /* { dg-final { scan-assembler "f8:\n\trisbg\t%r2,%r3,8,63,64-8" { target { lp64 } } } } */ - /* With -m31 risbg is not really useful here, so do not test for it. */ + /* { dg-final { scan-assembler "f8:\n\trisbg\t%r2,%r3,8,63,64-8" } } */ i64 v_anda = v_a & -72057594037927936; i64 v_shrb = ((ui64)v_b) >> 8; i64 v_or = v_anda | v_shrb; @@ -100,8 +96,7 @@ i64 f8 (i64 v_a, i64 v_b) // ands with complement masks. i32 f9 (i64 v_x, i32 v_y) { - /* { dg-final { scan-assembler "f9:\n\trisbg\t%r3,%r2,48,63,64-48" { target { lp64 } }} } */ - /* { dg-final { scan-assembler "f9:\n\trisbg\t%r4,%r2,32\\+16,63,64-16" { target { ! lp64 } }} } */ + /* { dg-final { scan-assembler "f9:\n\trisbg\t%r3,%r2,48,63,64-48" } } */ i64 v_shr6 = ((ui64)v_x) >> 48; i32 v_conv = (ui32)v_shr6; i32 v_and1 = v_y & -65536; @@ -113,8 +108,7 @@ i32 f9 (i64 v_x, i32 v_y) // ands with incompatible masks. i32 f10 (i64 v_x, i32 v_y) { - /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" } } */ i64 v_shr6 = ((ui64)v_x) >> 48; i32 v_conv = (ui32)v_shr6; i32 v_and1 = v_y & -16777216; diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c index 02f6e046eb9d..e3795e0f8aa0 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c @@ -2,7 +2,7 @@ /* Tests ported from the Llvm testsuite. */ -/* { dg-do compile { target s390x-*-* } } */ +/* { dg-do compile } */ /* { dg-options "-O3 -march=zEC12 -mzarch -fno-asynchronous-unwind-tables" } */ #define i64 signed long long @@ -11,8 +11,7 @@ // On zEC12, we generally prefer RISBGN. i64 f1 (i64 v_a, i64 v_b) { -/* { dg-final { scan-assembler "f1:\n\trisbgn\t%r2,%r3,60,62,0" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "f1:\n\trisbgn\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbgn\t%r3,%r5,60,62,0\n" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "f1:\n\trisbgn\t%r2,%r3,60,62,0" } } */ i64 v_anda = v_a & -15; i64 v_andb = v_b & 14; i64 v_or = v_anda | v_andb; @@ -23,8 +22,7 @@ i64 f1 (i64 v_a, i64 v_b) extern i64 f2_foo(); i64 f2 (i64 v_a, i64 v_b) { -/* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r3,60,62,0\n\tbner\t%r14\n\tjg\tf2_foo.*\n" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "f2:\n\trisbgn\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r3,%r5,60,62,0" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "f2:\n\trisbg\t%r2,%r3,60,62,0\n\tbner\t%r14\n\tjg\tf2_foo.*\n" } } */ i64 v_anda = v_a & -15; i64 v_andb = v_b & 14; i64 v_or = v_anda | v_andb; @@ -37,8 +35,7 @@ i64 f2 (i64 v_a, i64 v_b) void f2_bar (); void f2_cconly (i64 v_a, i64 v_b) { -/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r2,%r3,60,62,0\n\tber\t%r14\n\tjg\tf2_bar(@PLT)?\n" { target { lp64 } } } } */ -/* { dg-final { scan-assembler "f2_cconly:\n\trisbgn\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r3,%r5,60,62,0\n\tber\t%r14\n\tjg\tf2_bar(@PLT)?\n" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r2,%r3,60,62,0\n\tber\t%r14\n\tjg\tf2_bar(@PLT)?\n" } } */ if ((v_a & -15) | (v_b & 14)) f2_bar(); } diff --git a/gcc/testsuite/gcc.target/s390/stack-clash-4.c b/gcc/testsuite/gcc.target/s390/stack-clash-4.c deleted file mode 100644 index 619d99ddf691..000000000000 --- a/gcc/testsuite/gcc.target/s390/stack-clash-4.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O1 -m31 -mzarch -fstack-clash-protection" } */ - -extern void c(char*); - -void -a() { - char *b = __builtin_alloca(3); - c(b); -} diff --git a/gcc/testsuite/gcc.target/s390/stack-clash-5.c b/gcc/testsuite/gcc.target/s390/stack-clash-5.c deleted file mode 100644 index 81e202e2aab6..000000000000 --- a/gcc/testsuite/gcc.target/s390/stack-clash-5.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O1 -m31 -mzarch -fstack-clash-protection" } */ - -extern void bar (char*); - -void -foo() { - char a[4000]; - bar (a) ; -} diff --git a/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c index 1efd24551443..b71ff2cf535e 100644 --- a/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c +++ b/gcc/testsuite/gcc.target/s390/stack-protector-guard-tls-1.c @@ -1,12 +1,9 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fstack-protector-all" } */ -/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 8 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\tsllg\t%r[0-9]+,%r[0-9]+,32} 4 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 3 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times {\tmvc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\tmvc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times {\tclc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {\tclc\t100\(4,%r15\),20\(%r[0-9]+\)} 2 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {\tear\t%r[0-9]+,%a[01]} 8 } } */ +/* { dg-final { scan-assembler-times {\tsllg\t%r[0-9]+,%r[0-9]+,32} 4 } } */ +/* { dg-final { scan-assembler-times {\tmvc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 } } */ +/* { dg-final { scan-assembler-times {\tclc\t160\(8,%r15\),40\(%r[0-9]+\)} 2 } } */ /* Computing the address of the thread pointer on s390 involves multiple instructions and therefore bears the risk that the address of the canary or diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-12.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-12.c index a22a3e110185..5a3b8366ff63 100644 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-12.c +++ b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-12.c @@ -10,8 +10,7 @@ void da(int x) { bar(x); bar(x + 1); - /* { dg-final { scan-assembler-times "\ttmll\t%r15,256" 2 { target { lp64 } } } } */ - /* { dg-final { scan-assembler-times "\ttml\t%r15,384" 2 { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler-times "\ttmll\t%r15,256" 2 } } */ } #pragma GCC target("stack-size=1024,stack-guard=0") @@ -19,8 +18,7 @@ void p1(int x) { bar(x); bar(x + 1); - /* { dg-final { scan-assembler-times "\ttmll\t%r15,768" 1 { target { lp64 } } } } */ - /* { dg-final { scan-assembler-times "\ttml\t%r15,896" 1 { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler-times "\ttmll\t%r15,768" 1 } } */ } #pragma GCC reset_options @@ -29,8 +27,7 @@ void p0(int x) { bar(x); bar(x + 1); - /* { dg-final { scan-assembler-times "\ttmll\t%r15,1792" 1 { target { lp64 } } } } */ - /* { dg-final { scan-assembler-times "\ttml\t%r15,1920" 1 { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler-times "\ttmll\t%r15,1792" 1 } } */ } #pragma GCC reset_options @@ -39,8 +36,7 @@ void a1(int x) { bar(x); bar(x + 1); - /* { dg-final { scan-assembler-times "\ttmll\t%r15,3840" 1 { target { lp64 } } } } */ - /* { dg-final { scan-assembler-times "\ttml\t%r15,3968" 1 { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler-times "\ttmll\t%r15,3840" 1 } } */ } __attribute__ ((target("stack-size=8192,stack-guard=0"))) @@ -48,8 +44,7 @@ void a0(int x) { bar(x); bar(x + 1); - /* { dg-final { scan-assembler-times "\ttmll\t%r15,7936" 1 { target { lp64 } } } } */ - /* { dg-final { scan-assembler-times "\ttml\t%r15,8064" 1 { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler-times "\ttmll\t%r15,7936" 1 } } */ } void d(int x) diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-15.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-15.c index dd0c978936b8..55b7f2756450 100644 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-15.c +++ b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-15.c @@ -111,7 +111,5 @@ int a0h(void) return 8; } -/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -40" 10 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -8" 5 { target { lp64 } } } } */ -/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -36" 10 { target { ! lp64 } } } } */ -/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -4" 5 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -40" 10 } } */ +/* { dg-final { scan-assembler-times "\t.cfi_offset 15, -8" 5 } } */ diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-1.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-1.c deleted file mode 100644 index 3247fff902b1..000000000000 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-1.c +++ /dev/null @@ -1,353 +0,0 @@ -/* Functional tests for the "target" attribute and pragma. */ - -/* { dg-do assemble { target { ! lp64 } } } */ -/* { dg-require-effective-target target_attribute } */ -/* { dg-options "-save-temps -mdebug -m31 -march=z13 -mtune=z10 -mstack-size=4096 -mstack-guard=0 -mbranch-cost=2 -mwarn-framesize=0 -mhard-dfp -mno-backchain -mhard-float -mno-vx -mhtm -mpacked-stack -mno-small-exec -mzvector -mno-mvcle -mzarch -mwarn-dynamicstack" } */ - -/** - ** - ** Start - ** - **/ - -void fn_default_start (void) { } -/* { dg-final { scan-assembler "fn:fn_default_start ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start se0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wd1" } } */ - -/** - ** - ** Attribute - ** - **/ - -__attribute__ ((target ("arch=z13"))) -void fn_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wd1" } } */ - -void fn_att_1_default (void) { } - -__attribute__ ((target ("arch=z10"))) -void fn_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wd1" } } */ - -void fn_att_0_default (void) { } - -__attribute__ ((target ("arch=z10,arch=z13"))) -void fn_att_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wd1" } } */ - -__attribute__ ((target ("arch=z13,arch=z10"))) -void fn_att_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wd1" } } */ - -/** - ** - ** Pragma - ** - **/ - -#pragma GCC target ("arch=z13") -void fn_pragma_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wd1" } } */ -#pragma GCC reset_options - -void fn_pragma_1_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wd1" } } */ - -#pragma GCC target ("arch=z10") -void fn_pragma_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wd1" } } */ -#pragma GCC reset_options - -void fn_pragma_0_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wd1" } } */ - -#pragma GCC target ("arch=z10") -#pragma GCC target ("arch=z13") -void fn_pragma_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("arch=z13") -#pragma GCC target ("arch=z10") -void fn_pragma_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wd1" } } */ -#pragma GCC reset_options - -/** - ** - ** Pragma and attribute - ** - **/ - -#pragma GCC target ("arch=z13") -__attribute__ ((target ("arch=z13"))) -void fn_pragma_1_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("arch=z13") -__attribute__ ((target ("arch=z13"))) -void fn_pragma_0_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("arch=z13") -__attribute__ ((target ("arch=z10"))) -void fn_pragma_1_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("arch=z13") -__attribute__ ((target ("arch=z10"))) -void fn_pragma_0_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wd1" } } */ -#pragma GCC reset_options - -/** - ** - ** End - ** - **/ - -void fn_default_end (void) { } -/* { dg-final { scan-assembler "fn:fn_default_end ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end se0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wd1" } } */ diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-10.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-10.c deleted file mode 100644 index f1beb1d8773e..000000000000 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-10.c +++ /dev/null @@ -1,353 +0,0 @@ -/* Functional tests for the "target" attribute and pragma. */ - -/* { dg-do assemble { target { ! lp64 } } } */ -/* { dg-require-effective-target target_attribute } */ -/* { dg-options "-save-temps -mdebug -m31 -march=z10 -mtune=z13 -mstack-size=2048 -mstack-guard=16 -mbranch-cost=1 -mwarn-framesize=512 -mno-hard-dfp -mbackchain -msoft-float -mno-vx -mno-htm -mno-packed-stack -msmall-exec -mno-zvector -mmvcle -mesa -mno-warn-dynamicstack" } */ - -/** - ** - ** Start - ** - **/ - -void fn_default_start (void) { } -/* { dg-final { scan-assembler "fn:fn_default_start ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start se1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wd0" } } */ - -/** - ** - ** Attribute - ** - **/ - -__attribute__ ((target ("branch-cost=1"))) -void fn_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wd0" } } */ - -void fn_att_0_default (void) { } - -__attribute__ ((target ("branch-cost=2"))) -void fn_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wd0" } } */ - -void fn_att_1_default (void) { } - -__attribute__ ((target ("branch-cost=2,branch-cost=1"))) -void fn_att_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wd0" } } */ - -__attribute__ ((target ("branch-cost=1,branch-cost=2"))) -void fn_att_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wd0" } } */ - -/** - ** - ** Pragma - ** - **/ - -#pragma GCC target ("branch-cost=1") -void fn_pragma_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wd0" } } */ -#pragma GCC reset_options - -void fn_pragma_0_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wd0" } } */ - -#pragma GCC target ("branch-cost=2") -void fn_pragma_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wd0" } } */ -#pragma GCC reset_options - -void fn_pragma_1_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wd0" } } */ - -#pragma GCC target ("branch-cost=2") -#pragma GCC target ("branch-cost=1") -void fn_pragma_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wd0" } } */ -#pragma GCC reset_options - -#pragma GCC target ("branch-cost=1") -#pragma GCC target ("branch-cost=2") -void fn_pragma_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wd0" } } */ -#pragma GCC reset_options - -/** - ** - ** Pragma and attribute - ** - **/ - -#pragma GCC target ("branch-cost=1") -__attribute__ ((target ("branch-cost=1"))) -void fn_pragma_0_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wd0" } } */ -#pragma GCC reset_options - -#pragma GCC target ("branch-cost=1") -__attribute__ ((target ("branch-cost=1"))) -void fn_pragma_1_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wd0" } } */ -#pragma GCC reset_options - -#pragma GCC target ("branch-cost=1") -__attribute__ ((target ("branch-cost=2"))) -void fn_pragma_0_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wd0" } } */ -#pragma GCC reset_options - -#pragma GCC target ("branch-cost=1") -__attribute__ ((target ("branch-cost=2"))) -void fn_pragma_1_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wd0" } } */ -#pragma GCC reset_options - -/** - ** - ** End - ** - **/ - -void fn_default_end (void) { } -/* { dg-final { scan-assembler "fn:fn_default_end ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end se1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wd0" } } */ diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-11.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-11.c deleted file mode 100644 index d459eec258f5..000000000000 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-11.c +++ /dev/null @@ -1,353 +0,0 @@ -/* Functional tests for the "target" attribute and pragma. */ - -/* { dg-do assemble { target { ! lp64 } } } */ -/* { dg-require-effective-target target_attribute } */ -/* { dg-options "-save-temps -mdebug -m31 -march=z13 -mtune=z10 -mstack-size=4096 -mstack-guard=0 -mbranch-cost=2 -mwarn-framesize=0 -mhard-dfp -mno-backchain -mhard-float -mvx -mhtm -mpacked-stack -mno-small-exec -mzvector -mno-mvcle -mzarch -mwarn-dynamicstack" } */ - -/** - ** - ** Start - ** - **/ - -void fn_default_start (void) { } -/* { dg-final { scan-assembler "fn:fn_default_start ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start se0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wd1" } } */ - -/** - ** - ** Attribute - ** - **/ - -__attribute__ ((target ("warn-framesize=512"))) -void fn_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wd1" } } */ - -void fn_att_1_default (void) { } - -__attribute__ ((target ("warn-framesize=0"))) -void fn_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wd1" } } */ - -void fn_att_0_default (void) { } - -__attribute__ ((target ("warn-framesize=0,warn-framesize=512"))) -void fn_att_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wd1" } } */ - -__attribute__ ((target ("warn-framesize=512,warn-framesize=0"))) -void fn_att_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wd1" } } */ - -/** - ** - ** Pragma - ** - **/ - -#pragma GCC target ("warn-framesize=512") -void fn_pragma_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wd1" } } */ -#pragma GCC reset_options - -void fn_pragma_1_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wd1" } } */ - -#pragma GCC target ("warn-framesize=0") -void fn_pragma_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wd1" } } */ -#pragma GCC reset_options - -void fn_pragma_0_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wd1" } } */ - -#pragma GCC target ("warn-framesize=0") -#pragma GCC target ("warn-framesize=512") -void fn_pragma_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("warn-framesize=512") -#pragma GCC target ("warn-framesize=0") -void fn_pragma_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wd1" } } */ -#pragma GCC reset_options - -/** - ** - ** Pragma and attribute - ** - **/ - -#pragma GCC target ("warn-framesize=512") -__attribute__ ((target ("warn-framesize=512"))) -void fn_pragma_1_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("warn-framesize=512") -__attribute__ ((target ("warn-framesize=512"))) -void fn_pragma_0_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("warn-framesize=512") -__attribute__ ((target ("warn-framesize=0"))) -void fn_pragma_1_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wd1" } } */ -#pragma GCC reset_options - -#pragma GCC target ("warn-framesize=512") -__attribute__ ((target ("warn-framesize=0"))) -void fn_pragma_0_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 se0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wd1" } } */ -#pragma GCC reset_options - -/** - ** - ** End - ** - **/ - -void fn_default_end (void) { } -/* { dg-final { scan-assembler "fn:fn_default_end ar7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end tu4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ss4096" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end sg0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end bc2" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hd1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ba0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end hf1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end vx1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ht1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end ps1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end se0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end zv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end mv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_end wd1" } } */ diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-12.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-12.c deleted file mode 100644 index 8868f91df52f..000000000000 --- a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-12.c +++ /dev/null @@ -1,353 +0,0 @@ -/* Functional tests for the "target" attribute and pragma. */ - -/* { dg-do assemble { target { ! lp64 } } } */ -/* { dg-require-effective-target target_attribute } */ -/* { dg-options "-save-temps -mdebug -m31 -march=z10 -mtune=z13 -mstack-size=2048 -mstack-guard=16 -mbranch-cost=1 -mwarn-framesize=512 -mno-hard-dfp -mbackchain -msoft-float -mno-vx -mno-htm -mno-packed-stack -msmall-exec -mno-zvector -mmvcle -mesa -mno-warn-dynamicstack" } */ - -/** - ** - ** Start - ** - **/ - -void fn_default_start (void) { } -/* { dg-final { scan-assembler "fn:fn_default_start ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start se1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_default_start wd0" } } */ - -/** - ** - ** Attribute - ** - **/ - -__attribute__ ((target ("warn-framesize=0"))) -void fn_att_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0 wd0" } } */ - -void fn_att_0_default (void) { } - -__attribute__ ((target ("warn-framesize=512"))) -void fn_att_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1 wd0" } } */ - -void fn_att_1_default (void) { } - -__attribute__ ((target ("warn-framesize=512,warn-framesize=0"))) -void fn_att_1_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_1_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_1_0 wd0" } } */ - -__attribute__ ((target ("warn-framesize=0,warn-framesize=512"))) -void fn_att_0_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_att_0_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_att_0_1 wd0" } } */ - -/** - ** - ** Pragma - ** - **/ - -#pragma GCC target ("warn-framesize=0") -void fn_pragma_0 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0 wf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0 wd0" } } */ -#pragma GCC reset_options - -void fn_pragma_0_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_0_default wd0" } } */ - -#pragma GCC target ("warn-framesize=512") -void fn_pragma_1 (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1 wf512" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hd0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ba1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 hf0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 vx0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ht0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 ps0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 se1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 zv0" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 mv1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1 wd0" } } */ -#pragma GCC reset_options - -void fn_pragma_1_default (void) { } -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ar4" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default tu7" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default ss2048" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default sg16" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default bc1" } } */ -/* { dg-final { scan-assembler "fn:fn_pragma_1_default wf512" } } */ -/* { dg-final { scan-asse[...] [diff truncated at 524288 bytes]