[gcc r17-2343] RISC-V: Remove scratch register from bitfield extract splitter

https://gcc.gnu.org/g:f06e56614b948ad88dabf63020f47713b7dea0ec

commit r17-2343-gf06e56614b948ad88dabf63020f47713b7dea0ec
Author: Jin Ma <[email protected]>
Date:   Fri Jul 10 17:43:40 2026 +0800

    RISC-V: Remove scratch register from bitfield extract splitter
    
    The early-clobber scratch in *<any_extract>3 is unnecessary: slli
    reads its source before writing, so the destination register can
    safely hold the intermediate value.  This reduces register pressure
    and makes the split output simpler.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (*<any_extract:optab><GPR:mode>3):
            Remove (clobber (match_scratch)) and use operand 0 as the
            intermediate destination for the shift-left half of the split.

Diff:
---
 gcc/config/riscv/riscv.md | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2cd26fa99abc..f10a08460acf 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3157,8 +3157,7 @@
 	 (any_extract:GPR
        (match_operand:GPR 1 "register_operand" " r")
        (match_operand     2 "const_int_operand")
-       (match_operand     3 "const_int_operand")))
-   (clobber (match_scratch:GPR  4 "=&r"))]
+       (match_operand     3 "const_int_operand")))]
   "!((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZICOND
       || TARGET_XVENTANACONDOPS || TARGET_SFB_ALU)
      && (INTVAL (operands[2]) == 1))
@@ -3169,10 +3168,10 @@
         && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
   "#"
   "&& reload_completed"
-  [(set (match_dup 4)
+  [(set (match_dup 0)
      (ashift:GPR (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
-     (<extract_shift>:GPR (match_dup 4) (match_dup 3)))]
+     (<extract_shift>:GPR (match_dup 0) (match_dup 3)))]
 {
   int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant ();
   int sizebits = INTVAL (operands[2]);