[gcc r17-2376] RISC-V: Allow RVV register overlap for v[sz]ext.vf8

https://gcc.gnu.org/g:d440d4eeae8a3b295403684c3d34c8d961704950

commit r17-2376-gd440d4eeae8a3b295403684c3d34c8d961704950
Author: Pan Li <[email protected]>
Date:   Sat Jul 11 22:32:59 2026 +0800

    RISC-V: Allow RVV register overlap for v[sz]ext.vf8
    
    Like v[sz]ext.vf4, allow the rvv register overlap
    for v[sz]ext.vf8.
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Leverage Wvr constraint.
    
    Signed-off-by: Pan Li <[email protected]>

Diff:
---
 gcc/config/riscv/vector.md | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a5ebc85b764e..dca6108e0aaa 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4130,19 +4130,19 @@
 
 ;; Vector Oct-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf8"
-  [(set (match_operand:VOEXTI 0 "register_operand"         "=&vr,&vr")
+  [(set (match_operand:VOEXTI 0 "register_operand"            "=vr,  vr,  vd,  vd")
 	(if_then_else:VOEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	     (match_operand 4 "vector_length_operand"         "  rvl,  rvl")
-	     (match_operand 5 "const_int_operand"             "    i,    i")
-	     (match_operand 6 "const_int_operand"             "    i,    i")
-	     (match_operand 7 "const_int_operand"             "    i,    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"      "Wc1, Wc1,  vm,  vm")
+	     (match_operand 4 "vector_length_operand"         "rvl, rvl, rvl, rvl")
+	     (match_operand 5 "const_int_operand"             "  i,   i,   i,   i")
+	     (match_operand 6 "const_int_operand"             "  i,   i,   i,   i")
+	     (match_operand 7 "const_int_operand"             "  i,   i,   i,   i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_extend:VOEXTI
-	    (match_operand:<V_OCT_TRUNC> 3 "register_operand" "   vr,   vr"))
-	  (match_operand:VOEXTI 2 "vector_merge_operand"      "   vu,    0")))]
+	    (match_operand:<V_OCT_TRUNC> 3 "register_operand" "Wvr, Wvr, Wvr, Wvr"))
+	  (match_operand:VOEXTI 2 "vector_merge_operand"      " vu,   0,  vu,   0")))]
   "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "v<sz>ext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")