[gcc r17-2434] x86-64: Add *fix_trunc<mode>si_sse_2_zext

https://gcc.gnu.org/g:368ef32ae78804c7c4fc8f021db337e0e63576b2

commit r17-2434-g368ef32ae78804c7c4fc8f021db337e0e63576b2
Author: H.J. Lu <[email protected]>
Date:   Thu Jul 16 07:30:31 2026 +0800

    x86-64: Add *fix_trunc<mode>si_sse_2_zext
    
    We expand
    
    unsigned long long
    func (float x)
    {
      return (unsigned int) x;
    }
    
    to
    
    (insn 6 5 7 (set (reg:DI 103)
            (fix:DI (reg/v:SF 100 [ x ]))) "x.c":4:10 -1
         (nil))
    
    (insn 7 6 8 (set (reg:SI 102 [ _1 ])
            (subreg:SI (reg:DI 103) 0)) "x.c":4:10 -1
         (nil))
    
    (insn 8 7 9 (set (reg:DI 101 [ _3 ])
            (zero_extend:DI (reg:SI 102 [ _1 ]))) "x.c":4:10 -1
         (nil))
    
    Add *fix_trunc<mode>si_sse_2_zext so that combine can generate:
    
    (insn 8 6 13 2 (set (reg:DI 101 [ _3 ])
            (zero_extend:DI (subreg:SI (fix:DI (reg:SF 104 [ x ])) 0))) "x.c":4:10 235 {*fix_truncsfsi_sse_2_zext}
         (expr_list:REG_DEAD (reg:SF 104 [ x ])
            (nil)))
    
    This fixes
    
    FAIL: gcc.target/i386/zext-sse-1.c check-function-bodies func1
    FAIL: gcc.target/i386/zext-sse-1.c check-function-bodies func2
    
            PR target/126231
            * config/i386/i386.md (*fix_trunc<mode>si_sse_2_zext): New.
    
    Signed-off-by: H.J. Lu <[email protected]>

Diff:
---
 gcc/config/i386/i386.md | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f6bfde1f4eda..3aa8c9260942 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6084,6 +6084,23 @@
    (set_attr "amdfam10_decode" "double,double")
    (set_attr "bdver1_decode" "double,double")])
 
+(define_insn "*fix_trunc<mode>si_sse_2_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (zero_extend:DI
+          (subreg:SI
+            (fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "v,m")) 0)))]
+  "TARGET_64BIT
+   && SSE_FLOAT_MODE_P (<MODE>mode)
+   && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+  "%vcvtt<ssemodesuffix>2si{l}\t{%1, %k0|%k0, %1}"
+  [(set_attr "type" "sseicvt")
+   (set_attr "prefix" "maybe_vex")
+   (set_attr "prefix_rex" "*")
+   (set_attr "mode" "<MODE>")
+   (set_attr "athlon_decode" "double,vector")
+   (set_attr "amdfam10_decode" "double,double")
+   (set_attr "bdver1_decode" "double,double")])
+
 ;; Avoid vector decoded forms of the instruction.
 (define_peephole2
   [(match_scratch:MODEF 2 "x")