[gcc(refs/vendors/ibm/heads/dmr-mainline)] MMA+: Add int8 and bfloat16 ger builtins

https://gcc.gnu.org/g:10b8cd4114449ee3431b7ac438bef14d876f80f9

commit 10b8cd4114449ee3431b7ac438bef14d876f80f9
Author: Kishan Parmar <[email protected]>
Date:   Thu Jul 9 14:37:32 2026 +0530

    MMA+: Add int8 and bfloat16 ger builtins
    
    Add builtins __builtin_mma_dmxvbf16gerx2, __builtin_mma_dmxvbf16gerx2nn,
    __builtin_mma_mxvbf16gerx2np, __builtin_mma_dmxvbf16gerx2pn,
    __builtin_mma_dmxvbf16gerx2pp, __builtin_mma_pmdmxvbf16gerx2,
    __builtin_mma_pmdmxvbf16gerx2nn, __builtin_mma_pmdmxvbf16gerx2np,
    __builtin_mma_pmdmxvbf16gerx2pn, __builtin_mma_pmdmxvbf16gerx2pp,
    __builtin_mma_dmxvi8gerx4spp, __builtin_mma_pmdmxvi8gerx4spp

Diff:
---
 gcc/config/rs6000/mma.md                         |  98 +++++++++--
 gcc/config/rs6000/rs6000-builtins.def            |  84 ++++++++++
 gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c | 203 +++++++++++++++++++++++
 3 files changed, 374 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 01bd708fbdc7..890166642101 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -103,6 +103,18 @@
    UNSPEC_DMF_PMDMXVI8GERX4
    UNSPEC_DMF_PMDMXVI8GERX4PP
    UNSPEC_DMF_DMSETDMRZ
+   UNSPEC_DMF_DMXVI8GERX4SPP
+   UNSPEC_DMF_PMDMXVI8GERX4SPP
+   UNSPEC_DMF_DMXVBF16GERX2
+   UNSPEC_DMF_DMXVBF16GERX2PP
+   UNSPEC_DMF_DMXVBF16GERX2PN
+   UNSPEC_DMF_DMXVBF16GERX2NP
+   UNSPEC_DMF_DMXVBF16GERX2NN
+   UNSPEC_DMF_PMDMXVBF16GERX2
+   UNSPEC_DMF_PMDMXVBF16GERX2PP
+   UNSPEC_DMF_PMDMXVBF16GERX2PN
+   UNSPEC_DMF_PMDMXVBF16GERX2NP
+   UNSPEC_DMF_PMDMXVBF16GERX2NN
   ])
 
 (define_c_enum "unspecv"
@@ -146,7 +158,8 @@
 (define_int_iterator MMA_PV		[UNSPEC_MMA_XVF64GER])
 
 ; DMF instructions with 1 vector pair and 1 vector arguments
-(define_int_iterator DMF_PV		[UNSPEC_DMF_DMXVI8GERX4])
+(define_int_iterator DMF_PV		[UNSPEC_DMF_DMXVI8GERX4
+					 UNSPEC_DMF_DMXVBF16GERX2])
 
 ;; MMA instructions with 1 accumulator, 1 vector pair and 1 vector arguments
 (define_int_iterator MMA_APV		[UNSPEC_MMA_XVF64GERPP
@@ -155,7 +168,12 @@
 					 UNSPEC_MMA_XVF64GERNN])
 
 ;; DMF instructions with 1 dmr, 1 vector pair and 1 vector arguments
-(define_int_iterator DMF_DPV		[UNSPEC_DMF_DMXVI8GERX4PP])
+(define_int_iterator DMF_DPV		[UNSPEC_DMF_DMXVI8GERX4PP
+					 UNSPEC_DMF_DMXVI8GERX4SPP
+					 UNSPEC_DMF_DMXVBF16GERX2PP
+					 UNSPEC_DMF_DMXVBF16GERX2PN
+					 UNSPEC_DMF_DMXVBF16GERX2NP
+					 UNSPEC_DMF_DMXVBF16GERX2NN])
 
 ;; MMA instructions with 2 vector, 2 4-bit and 1 8-bit arguments
 (define_int_iterator MMA_VVI4I4I8	[UNSPEC_MMA_PMXVI4GER8])
@@ -212,7 +230,19 @@
 
 ;; DMF instructions with 1 dmr, 1 vector pair, 1 vector and 1 8-bit and
 ;; 2 4-bit arguments
-(define_int_iterator DMF_DPVI8I4I4	[UNSPEC_DMF_PMDMXVI8GERX4PP])
+(define_int_iterator DMF_DPVI8I4I4	[UNSPEC_DMF_PMDMXVI8GERX4PP
+					 UNSPEC_DMF_PMDMXVI8GERX4SPP])
+
+;; DMF instructions with 1 vector pair, 1 vector, 1 8-bit, 1 4-bit
+;; and 1 2-bit arguments
+(define_int_iterator DMF_PVI8I4I2      [UNSPEC_DMF_PMDMXVBF16GERX2])
+
+;; DMF instructions with 1dmr, 1 vector pair, 1 vector, 1 8-bit,
+;; 1 4-bit and 1 2-bit arguments
+(define_int_iterator DMF_DPVI8I4I2     [UNSPEC_DMF_PMDMXVBF16GERX2PP
+					UNSPEC_DMF_PMDMXVBF16GERX2PN
+					UNSPEC_DMF_PMDMXVBF16GERX2NP
+					UNSPEC_DMF_PMDMXVBF16GERX2NN])
 
 (define_int_attr acc		[(UNSPEC_MMA_XXMFACC		"xxmfacc")
 				 (UNSPEC_MMA_XXMTACC		"xxmtacc")])
@@ -244,13 +274,20 @@
 				 (UNSPEC_MMA_XVF32GERNN		"xvf32gernn")])
 
 (define_int_attr pv		[(UNSPEC_MMA_XVF64GER		"xvf64ger")
-				 (UNSPEC_DMF_DMXVI8GERX4        "dmxvi8gerx4")])
+				 (UNSPEC_DMF_DMXVI8GERX4        "dmxvi8gerx4")
+				 (UNSPEC_DMF_DMXVBF16GERX2      "dmxvbf16gerx2")])
 
 (define_int_attr apv		[(UNSPEC_MMA_XVF64GERPP		"xvf64gerpp")
 				 (UNSPEC_MMA_XVF64GERPN		"xvf64gerpn")
 				 (UNSPEC_MMA_XVF64GERNP		"xvf64gernp")
-				 (UNSPEC_MMA_XVF64GERNN		"xvf64gernn")
-				 (UNSPEC_DMF_DMXVI8GERX4PP      "dmxvi8gerx4pp")])
+				 (UNSPEC_MMA_XVF64GERNN		"xvf64gernn")])
+
+(define_int_attr dpv		[(UNSPEC_DMF_DMXVI8GERX4PP	"dmxvi8gerx4pp")
+				 (UNSPEC_DMF_DMXVI8GERX4SPP	"dmxvi8gerx4spp")
+				 (UNSPEC_DMF_DMXVBF16GERX2PP	"dmxvbf16gerx2pp")
+				 (UNSPEC_DMF_DMXVBF16GERX2PN	"dmxvbf16gerx2pn")
+				 (UNSPEC_DMF_DMXVBF16GERX2NP	"dmxvbf16gerx2np")
+				 (UNSPEC_DMF_DMXVBF16GERX2NN	"dmxvbf16gerx2nn")])
 
 (define_int_attr vvi4i4i8	[(UNSPEC_MMA_PMXVI4GER8		"pmxvi4ger8")])
 
@@ -293,7 +330,15 @@
 
 (define_int_attr pvi8i4i4	[(UNSPEC_DMF_PMDMXVI8GERX4      "pmdmxvi8gerx4")])
 
-(define_int_attr dpvi8i4i4	[(UNSPEC_DMF_PMDMXVI8GERX4PP    "pmdmxvi8gerx4pp")])
+(define_int_attr dpvi8i4i4	[(UNSPEC_DMF_PMDMXVI8GERX4PP    "pmdmxvi8gerx4pp")
+				 (UNSPEC_DMF_PMDMXVI8GERX4SPP   "pmdmxvi8gerx4spp")])
+
+(define_int_attr pvi8i4i2	[(UNSPEC_DMF_PMDMXVBF16GERX2	"pmdmxvbf16gerx2")])
+
+(define_int_attr dpvi8i4i2	[(UNSPEC_DMF_PMDMXVBF16GERX2PP "pmdmxvbf16gerx2pp")
+				 (UNSPEC_DMF_PMDMXVBF16GERX2PN  "pmdmxvbf16gerx2pn")
+				 (UNSPEC_DMF_PMDMXVBF16GERX2NP  "pmdmxvbf16gerx2np")
+				 (UNSPEC_DMF_PMDMXVBF16GERX2NN  "pmdmxvbf16gerx2nn")])
 
 ;; Vector pair support.  OOmode can only live in VSRs.
 (define_expand "movoo"
@@ -1048,15 +1093,15 @@
 }
   [(set_attr "type" "dmf")])
 
-(define_insn "dmf_<apv>"
-  [(set (match_operand:TDO 0 "accumulator_operand" "=wD")
-	(unspec:TDO [(match_operand:TDO 1 "accumulator_operand" "0")
+(define_insn "dmf_<dpv>"
+  [(set (match_operand:TDO 0 "dmr_register_operand" "=wD")
+	(unspec:TDO [(match_operand:TDO 1 "dmr_register_operand" "0")
 		     (match_operand:OO 2 "vsx_register_operand" "wa")
 		     (match_operand:V16QI 3 "vsx_register_operand" "wa")]
 		    DMF_DPV))]
   "TARGET_DMF"
 {
-  return "<apv> %0,%x2,%x3";
+  return "<dpv> %0,%x2,%x3";
 }
   [(set_attr "type" "dmf")])
 
@@ -1091,3 +1136,34 @@
   [(set_attr "type" "dmf")
    (set_attr "prefixed" "yes")])
 
+
+(define_insn "dmf_<pvi8i4i2>"
+  [(set (match_operand:TDO 0 "dmr_register_operand" "=wD")
+       (unspec:TDO [(match_operand:OO 1 "vsx_register_operand" "wa")
+                    (match_operand:V16QI 2 "vsx_register_operand" "wa")
+                    (match_operand:SI 3 "u8bit_cint_operand" "n")
+                    (match_operand:SI 4 "const_0_to_15_operand" "n")
+                    (match_operand:SI 5 "const_0_to_3_operand" "n")]
+                    DMF_PVI8I4I2))]
+  "TARGET_DMF"
+{
+  return "<pvi8i4i2> %0,%x1,%x2,%3,%4,%5";
+}
+  [(set_attr "type" "dmf")
+   (set_attr "prefixed" "yes")])
+
+(define_insn "dmf_<dpvi8i4i2>"
+  [(set (match_operand:TDO 0 "dmr_register_operand" "=wD")
+       (unspec:TDO [(match_operand:TDO 1 "dmr_register_operand" "0")
+                    (match_operand:OO 2 "vsx_register_operand" "wa")
+                    (match_operand:V16QI 3 "vsx_register_operand" "wa")
+                    (match_operand:SI 4 "u8bit_cint_operand" "n")
+                    (match_operand:SI 5 "const_0_to_15_operand" "n")
+                    (match_operand:SI 6 "const_0_to_3_operand" "n")]
+                    DMF_DPVI8I4I2))]
+  "TARGET_DMF"
+{
+  return "<dpvi8i4i2> %0,%x2,%x3,%4,%5,%6";
+}
+  [(set_attr "type" "dmf")
+   (set_attr "prefixed" "yes")])
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index f949db410634..6787b0a9b802 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -4142,6 +4142,12 @@
   dmr1024 __builtin_mma_dmxvi8gerx4pp_internal (dmr1024, v256, vuc);
     DMXVI8GERX4PP_INTERNAL dmf_dmxvi8gerx4pp {dm}
 
+  void __builtin_mma_dmxvi8gerx4spp (dmr1024 *, v256, vuc);
+    DMXVI8GERX4SPP nothing {dm,dmint,dmr}
+
+  dmr1024 __builtin_mma_dmxvi8gerx4spp_internal (dmr1024, v256, vuc);
+    DMXVI8GERX4SPP_INTERNAL dmf_dmxvi8gerx4spp {dm}
+
   void __builtin_mma_pmdmxvi8gerx4 (dmr1024 *, v256, vuc, const int<8>, \
                                    const int<4>, const int<4>);
     PMDMXVI8GERX4 nothing {dm,pair,dmint}
@@ -4159,3 +4165,81 @@
                                                 const int<4>);
     PMDMXVI8GERX4PP_INTERNAL dmf_pmdmxvi8gerx4pp {dm,pair}
 
+  void __builtin_mma_pmdmxvi8gerx4spp (dmr1024 *, v256, vuc, const int<8>, \
+                                     const int<4>, const int<4>);
+    PMDMXVI8GERX4SPP nothing {dm,pair,dmint,dmr}
+
+  dmr1024 __builtin_mma_pmdmxvi8gerx4spp_internal (dmr1024, v256, vuc, \
+                                                const int<8>, const int<4>, \
+                                                const int<4>);
+    PMDMXVI8GERX4SPP_INTERNAL dmf_pmdmxvi8gerx4spp {dm,pair}
+
+  void __builtin_mma_dmxvbf16gerx2 (dmr1024 *, v256, vuc);
+    DMXVBF16GERX2 nothing {dm,dmint}
+
+  dmr1024 __builtin_mma_dmxvbf16gerx2_internal (v256, vuc);
+    DMXVBF16GERX2_INTERNAL dmf_dmxvbf16gerx2 {dm}
+
+  void __builtin_mma_dmxvbf16gerx2pp (dmr1024 *, v256, vuc);
+    DMXVBF16GERX2PP nothing {dm,dmint,dmr}
+
+  dmr1024 __builtin_mma_dmxvbf16gerx2pp_internal (dmr1024, v256, vuc);
+    DMXVBF16GERX2PP_INTERNAL dmf_dmxvbf16gerx2pp {dm}
+
+  void __builtin_mma_dmxvbf16gerx2pn (dmr1024 *, v256, vuc);
+    DMXVBF16GERX2PN nothing {dm,dmint,dmr}
+
+  dmr1024 __builtin_mma_dmxvbf16gerx2pn_internal (dmr1024, v256, vuc);
+    DMXVBF16GERX2PN_INTERNAL dmf_dmxvbf16gerx2pn {dm}
+
+  void __builtin_mma_dmxvbf16gerx2np (dmr1024 *, v256, vuc);
+    DMXVBF16GERX2NP nothing {dm,dmint,dmr}
+
+  dmr1024 __builtin_mma_dmxvbf16gerx2np_internal (dmr1024, v256, vuc);
+    DMXVBF16GERX2NP_INTERNAL dmf_dmxvbf16gerx2np {dm}
+
+  void __builtin_mma_dmxvbf16gerx2nn (dmr1024 *, v256, vuc);
+    DMXVBF16GERX2NN nothing {dm,dmint,dmr}
+
+  dmr1024 __builtin_mma_dmxvbf16gerx2nn_internal (dmr1024, v256, vuc);
+    DMXVBF16GERX2NN_INTERNAL dmf_dmxvbf16gerx2nn {dm}
+
+  void __builtin_mma_pmdmxvbf16gerx2 (dmr1024 *, v256, vuc, const int<8>, \
+                                   const int<4>, const int<2>);
+    PMDMXVBF16GERX2 nothing {dm,pair,dmint}
+
+  dmr1024 __builtin_mma_pmdmxvbf16gerx2_internal (v256, vuc, const int<8>, \
+                                              const int<4>, const int<2>);
+    PMDMXVBF16GERX2_INTERNAL dmf_pmdmxvbf16gerx2 {dm,pair}
+
+  void __builtin_mma_pmdmxvbf16gerx2pp (dmr1024 *, v256, vuc, const int<8>, \
+                                     const int<4>, const int<2>);
+    PMDMXVBF16GERX2PP nothing {dm,pair,dmint,dmr}
+
+  dmr1024 __builtin_mma_pmdmxvbf16gerx2pp_internal (dmr1024, v256, vuc, const int<8>, \
+                                                const int<4>, const int<2>);
+    PMDMXVBF16GERX2PP_INTERNAL dmf_pmdmxvbf16gerx2pp {dm,pair}
+
+  void __builtin_mma_pmdmxvbf16gerx2pn (dmr1024 *, v256, vuc, const int<8>, \
+                                     const int<4>, const int<2>);
+    PMDMXVBF16GERX2PN nothing {dm,pair,dmint,dmr}
+
+  dmr1024 __builtin_mma_pmdmxvbf16gerx2pn_internal (dmr1024, v256, vuc, const int<8>, \
+                                                const int<4>, const int<2>);
+    PMDMXVBF16GERX2PN_INTERNAL dmf_pmdmxvbf16gerx2pn {dm,pair}
+
+  void __builtin_mma_pmdmxvbf16gerx2np (dmr1024 *, v256, vuc, const int<8>, \
+                                     const int<4>, const int<2>);
+    PMDMXVBF16GERX2NP nothing {dm,pair,dmint,dmr}
+
+  dmr1024 __builtin_mma_pmdmxvbf16gerx2np_internal (dmr1024, v256, vuc, const int<8>, \
+                                                const int<4>, const int<2>);
+    PMDMXVBF16GERX2NP_INTERNAL dmf_pmdmxvbf16gerx2np {dm,pair}
+
+  void __builtin_mma_pmdmxvbf16gerx2nn (dmr1024 *, v256, vuc, const int<8>, \
+                                     const int<4>, const int<2>);
+    PMDMXVBF16GERX2NN nothing {dm,pair,dmint,dmr}
+
+  dmr1024 __builtin_mma_pmdmxvbf16gerx2nn_internal (dmr1024, v256, vuc, const int<8>, \
+                                                const int<4>, const int<2>);
+    PMDMXVBF16GERX2NN_INTERNAL dmf_pmdmxvbf16gerx2nn {dm,pair}
diff --git a/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
new file mode 100644
index 000000000000..ca712d7d3b06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/dmf-builtin-1.c
@@ -0,0 +1,203 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_compile_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+typedef unsigned char vec_t __attribute__((vector_size(16)));
+
+void
+foo (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvbf16gerx2 (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvbf16gerx2 (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2\M} 2 } } */
+
+void
+foo_1 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvbf16gerx2nn (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar_1 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvbf16gerx2nn (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2nn\M} 2 } } */
+
+void
+foo_2 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvbf16gerx2np (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar_2 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvbf16gerx2np (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2np\M} 2 } } */
+
+void
+foo_3 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvbf16gerx2pn (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar_3 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvbf16gerx2pn (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2pn\M} 2 } } */
+
+void
+foo_4 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvbf16gerx2pp (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar_4 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvbf16gerx2pp (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvbf16gerx2pp\M} 2 } } */
+
+void
+foo_5 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvbf16gerx2 (dst, vp, vec, 255, 15, 2);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2\M} 1 } } */
+
+void
+foo_6 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvbf16gerx2nn (dst, vp, vec, 255, 15, 2);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2nn\M} 1 } } */
+
+void
+foo_7 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvbf16gerx2np (dst, vp, vec, 255, 15, 2);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2np\M} 1 } } */
+
+void
+foo_8 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvbf16gerx2pn (dst, vp, vec, 255, 15, 2);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2pn\M} 1 } } */
+
+void
+foo_9 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvbf16gerx2pp (dst, vp, vec, 255, 15, 2);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvbf16gerx2pp\M} 1 } } */
+
+void
+foo_10 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_pmdmxvi8gerx4spp (dst, vp, vec, 255, 15, 15);
+}
+
+/* { dg-final { scan-assembler-times {\mpmdmxvi8gerx4spp\M} 1 } } */
+
+void
+foo_11 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_dmsetdmrz (&dmr);
+  __builtin_mma_dmxvi8gerx4spp (&dmr, vp, vec);
+  *dst = dmr;
+}
+
+void
+bar_11 (__dmr1024 *dst, __vector_pair *vpp, vec_t *src)
+{
+  __dmr1024 dmr = dst[0];;
+  __vector_pair vp = *vpp;
+  vec_t vec = *src;
+  __builtin_mma_dmxvi8gerx4spp (&dmr, vp, vec);
+  dst[1] = dmr;
+}
+
+/* { dg-final { scan-assembler-times {\mdmxvi8gerx4spp\M} 2 } } */