[gcc r17-2494] [PATCH] RISC-V: Remove zama16b from xt-c9501fdvt
Jeff Law via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
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https://gcc.gnu.org/g:ba0547444b747e775381b3db995f8fe8856ff5cc commit r17-2494-gba0547444b747e775381b3db995f8fe8856ff5cc Author: Wang Yaduo <[email protected]> Date: Fri Jul 17 07:08:16 2026 -0600 [PATCH] RISC-V: Remove zama16b from xt-c9501fdvt The binutils has not supported zama16b. Do not enable the extension through -mcpu=xt-c9501fdvt. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Remove zama16b from xt-c9501fdvt. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-xt-c9501fdvt.c: Expect __riscv_zama16b to be undefined. Signed-off-by: Wang Yaduo <[email protected]> Diff: --- gcc/config/riscv/riscv-cores.def | 2 +- gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 86d2175091ea..e7ae1cb934f0 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -166,7 +166,7 @@ RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_" "xt-c920v2") RISCV_CORE("xt-c9501fdvt", "rva23s64_zfbfmin_zfh_zicfilp_zicfiss_zkr_zmmul_" - "zbc_zca_zcd_zabha_zacas_zama16b_zvbc_zvfbfmin_" + "zbc_zca_zcd_zabha_zacas_zvbc_zvfbfmin_" "zvfbfwma_zvfh_zvkb_zvkg_zvkn_zvknc_zvkned_" "zvkng_zvknha_zvknhb_zvksc_zvksed_zvksg_zvksh_" "zvl256b_smaia_smcntrpmf_smcsrind_smepmp_smmpm_" diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c index 17e623fc5407..8e4eec7cb48f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c @@ -3,7 +3,7 @@ /* { dg-options "-mcpu=xt-c9501fdvt" { target { rv64 } } } */ /* XuanTie C950 => rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif _zicclsm_ziccrse_zicfilp_zicfiss_zicntr_zicond_zicsr_zifencei - _zihintntl_zihintpause_zihpm_zimop_za64rs_zabha_zacas_zama16b + _zihintntl_zihintpause_zihpm_zimop_za64rs_zabha_zacas _zawrs_zfa_zfbfmin_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs _zkr_zkt_zmmul_zvbb_zvbc_zvfbfmin_zvfbfwma_zvfh_zvfhmin_zvkb _zvkg_zvkn_zvknc_zvkned_zvkng_zvknha_zvknhb_zvksc_zvksed_zvksg @@ -45,7 +45,7 @@ && defined(__riscv_za64rs) \ && defined(__riscv_zabha) \ && defined(__riscv_zacas) \ - && defined(__riscv_zama16b) \ + && !defined(__riscv_zama16b) \ && defined(__riscv_zawrs) \ && defined(__riscv_zfa) \ && defined(__riscv_zfbfmin) \