[gcc(refs/users/meissner/heads/work251-dmf)] DMF patch 5

https://gcc.gnu.org/g:0f806f29eed46cc4c4e575aa30d1949cbac2c388

commit 0f806f29eed46cc4c4e575aa30d1949cbac2c388
Author: Michael Meissner <[email protected]>
Date:   Sat Jul 18 02:37:11 2026 -0400

    DMF patch 5
    
    Following patch has been bootstrapped and regtested on
    powerpc64le-linux-gnu. Ok for trunk and gcc-16?
    
    The future processor may introduce new set of registers for
    accumulators. This patch adds a constraint and predicate for the
    accumulator registers which can be used by the dense math and mma
    patterns.
    
    2026-07-16  Avinash Jayakar  <[email protected]>
    
    gcc/
    
            * config/rs6000/constraints.md
            (rs6000_constraints[RS6000_CONSTRAINT_wD]): New wD constraint.
            * config/rs6000/predicates.md (accumulator_operand): New predicate.
            * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Support wD
            register class.
            (rs6000_init_hard_regno_mode_ok): Map wD to FLOAT_REGS.
            * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wD constraint.
            * doc/md.texi: Document the new constraint.

Diff:
---
 gcc/config/rs6000/constraints.md |  4 ++++
 gcc/config/rs6000/predicates.md  | 18 ++++++++++++++++++
 gcc/config/rs6000/rs6000.cc      | 11 +++++++++--
 gcc/config/rs6000/rs6000.h       |  1 +
 gcc/doc/md.texi                  |  4 ++++
 5 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d0ed47faab84..4b2e703f0497 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -99,6 +99,10 @@
   "@internal Like @code{b}, if @option{-mpowerpc64} is used; otherwise,
    @code{NO_REGS}.")
 
+(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
+  "@internal Floating point register @code{FPR} if TARGET_MMA is enabled.
+  1024 bit Dense math register @code{DMR} if TARGET_DMF is enabled.")
+
 ;; wB needs ISA 2.07 VUPKHSW
 (define_constraint "wB"
   "@internal Signed 5-bit constant integer that can be loaded into an
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4162c22f8f68..9d4928b04642 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -163,6 +163,24 @@
   return VINT_REGNO_P (REGNO (op));
 })
 
+;; Return 1 if op is an accumulator.  On power10/11 systems, the accumulators
+;; overlap with the FPRs. If TARGET_DMF is true, it will be Dense math register.
+(define_predicate "accumulator_operand"
+  (match_operand 0 "register_operand")
+{
+  if (SUBREG_P (op))
+    op = SUBREG_REG (op);
+
+  if (!REG_P (op))
+    return 0;
+
+  if (!HARD_REGISTER_P (op))
+    return 1;
+
+  int r = REGNO (op);
+  return TARGET_DMF ? DMR_REGNO_P (r) : (FP_REGNO_P (r) && (r & 3) == 0);
+})
+
 ;; Return 1 if op is a vector register to do logical operations on (and, or,
 ;; xor, etc.)
 (define_predicate "vlogical_operand"
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index aed9c8e95fa1..a4b7762b0239 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2360,6 +2360,7 @@ rs6000_debug_reg_global (void)
 	   "wr reg_class = %s\n"
 	   "wx reg_class = %s\n"
 	   "wA reg_class = %s\n"
+	   "wD reg_class = %s\n"
 	   "\n",
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2367,7 +2368,8 @@ rs6000_debug_reg_global (void)
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
+	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
+	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
 
   nl = "\n";
   for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -3022,7 +3024,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 	wc - Reserved to represent individual CR bits (used in LLVM).
 	wn - always NO_REGS.
 	wr - GPR if 64-bit mode is permitted.
-	wx - Float register if we can do 32-bit int stores.  */
+	wx - Float register if we can do 32-bit int stores.
+	wD - Dense math register if TARGET_DMF is enabled, else float register.  */
 
   if (TARGET_HARD_FLOAT)
     rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
@@ -3030,6 +3033,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
     rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
   if (TARGET_VSX)
     rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
+  if (TARGET_DMF)
+    rs6000_constraints[RS6000_CONSTRAINT_wD] = DMR_REGS;
+  else if (TARGET_MMA)
+    rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
 
   if (TARGET_POWERPC64)
     {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index db4e55b7a1b4..bcd4c39d24dc 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1201,6 +1201,7 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wr,		/* GPR register if 64-bit  */
   RS6000_CONSTRAINT_wx,		/* FPR register for STFIWX */
   RS6000_CONSTRAINT_wA,		/* BASE_REGS if 64-bit.  */
+  RS6000_CONSTRAINT_wD,		/* Accumulator registers.  */
   RS6000_CONSTRAINT_MAX
 };
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index a98a572cc017..4253dc831e85 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3297,6 +3297,10 @@ Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
 @item wB
 Signed 5-bit constant integer that can be loaded into an Altivec register.
 
+@item wD
+Dense math register if @option{-mdense-math} is used; floating point register if
+@option{-mmma} with @option{-mno-dense-math}; otherwise, @code{NO_REGS}.
+
 @item wE
 Vector constant that can be loaded with the XXSPLTIB instruction.