[gcc r17-2506] RISC-V: Allow RVV register overlap for vfwcvt.x[u].f.v
Pan Li via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:13fa720ce146b00199ec7a8c5854efd6b0c1f101 commit r17-2506-g13fa720ce146b00199ec7a8c5854efd6b0c1f101 Author: Pan Li <[email protected]> Date: Thu Jul 16 12:55:25 2026 +0800 RISC-V: Allow RVV register overlap for vfwcvt.x[u].f.v Like v[sz]ext.vf8, allow the rvv register overlap for vfwcvt.x[u].f.v. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0ca589bf0420..cae98405a4ab 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7825,21 +7825,21 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWCONVERTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rvl, rvl") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI - [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] + [(match_operand:<VNCONVERT> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr")] VFCVTS) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwcvt.x<v_su>.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi")