[gcc r17-2524] RISC-V: Add minimal Smcdeleg extension support

https://gcc.gnu.org/g:320b40cca27e8983f3d290de110a3a06774850e5

commit r17-2524-g320b40cca27e8983f3d290de110a3a06774850e5
Author: Jiawei <[email protected]>
Date:   Wed Jun 24 21:43:16 2026 +0800

    RISC-V: Add minimal Smcdeleg extension support
    
    This adds minimal support for the Smcdeleg[1] (Machine-mode counter
    delegation) extension, which depends on Ssccfg.
    
    [1] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def (smcdeleg): Add new extension.
            * config/riscv/riscv-ext.opt: Ditto.
            * doc/riscv-ext.texi: Ditto.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/smcdeleg-version.c: New test.

Diff:
---
 gcc/config/riscv/riscv-ext.def                    | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                    |  2 ++
 gcc/doc/riscv-ext.texi                            |  4 ++++
 gcc/testsuite/gcc.target/riscv/smcdeleg-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index c10b0f295430..4159be567d2a 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1754,6 +1754,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smcdeleg,
+  /* UPPERCASE_NAME */ SMCDELEG,
+  /* FULL_NAME */ "Machine-mode counter delegation extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"ssccfg"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smcntrpmf,
   /* UPPERCASE_NAME */ SMCNTRPMF,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 79e1cce72e2b..cfee9551126c 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -359,6 +359,8 @@ Mask(SHVSATPA) Var(riscv_sh_subext)
 
 Mask(SMAIA) Var(riscv_sm_subext)
 
+Mask(SMCDELEG) Var(riscv_sm_subext)
+
 Mask(SMCNTRPMF) Var(riscv_sm_subext)
 
 Mask(SMCSRIND) Var(riscv_sm_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 41ba6831e8ed..d71ff736bef4 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -518,6 +518,10 @@
 @tab 1.0
 @tab Advanced interrupt architecture extension
 
+@item @samp{smcdeleg}
+@tab 1.0
+@tab Machine-mode counter delegation extension
+
 @item @samp{smcntrpmf}
 @tab 1.0
 @tab Cycle and instret privilege mode filtering
diff --git a/gcc/testsuite/gcc.target/riscv/smcdeleg-version.c b/gcc/testsuite/gcc.target/riscv/smcdeleg-version.c
new file mode 100644
index 000000000000..7acdc65c3029
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/smcdeleg-version.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_smcdeleg1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_smcdeleg1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_smcdeleg
+#error "Feature macro for 'smcdeleg' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*smcdeleg1p0" } } */