[gcc r17-2528] RISC-V: Add minimal Svrsw60t59b extension support

https://gcc.gnu.org/g:741dd3fa641a4506e5b138ba5de9eb45ebbf6888

commit r17-2528-g741dd3fa641a4506e5b138ba5de9eb45ebbf6888
Author: Jiawei <[email protected]>
Date:   Wed Jun 24 21:47:24 2026 +0800

    RISC-V: Add minimal Svrsw60t59b extension support
    
    This adds minimal support for the Svrsw60t59b[1] (Page-table reserved-for-
    software bits 60-59) extension, and it will be a new part of RVA23.1[2].
    
    [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/svrsw60t59b.adoc
    [2] https://github.com/riscv/riscv-isa-manual/pull/3170
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-ext.def (svrsw60t59b): Add new extension.
            * config/riscv/riscv-ext.opt: Ditto.
            * doc/riscv-ext.texi: Ditto.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/svrsw60t59b-version.c: New test.

Diff:
---
 gcc/config/riscv/riscv-ext.def                       | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                       |  2 ++
 gcc/doc/riscv-ext.texi                               |  4 ++++
 gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index a70d0abe343e..eeee99da77e2 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -2159,6 +2159,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ svrsw60t59b,
+  /* UPPERCASE_NAME */ SVRSW60T59B,
+  /* FULL_NAME */ "Page-table reserved-for-software bits 60-59 extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ svvptc,
   /* UPPERCASE_NAME */ SVVPTC,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 31b3a51a570e..8cd7825522b3 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -421,6 +421,8 @@ Mask(SVNAPOT) Var(riscv_sv_subext)
 
 Mask(SVPBMT) Var(riscv_sv_subext)
 
+Mask(SVRSW60T59B) Var(riscv_sv_subext)
+
 Mask(SVVPTC) Var(riscv_sv_subext)
 
 Mask(SVADU) Var(riscv_sv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 65b7c5197154..c3fc8c79118e 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -642,6 +642,10 @@
 @tab 1.0
 @tab Page-based memory types extension
 
+@item @samp{svrsw60t59b}
+@tab 1.0
+@tab Page-table reserved-for-software bits 60-59 extension
+
 @item @samp{svvptc}
 @tab 1.0
 @tab Extension for obviating memory-management instructions after marking PTEs valid
diff --git a/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c b/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c
new file mode 100644
index 000000000000..8d130fbd2339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_svrsw60t59b1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_svrsw60t59b1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_svrsw60t59b
+#error "Feature macro for 'svrsw60t59b' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*svrsw60t59b1p0" } } */