[gcc r15-11395] testsuite: arm: crypto-vsha1*_u32 tests got late-combine improvements

https://gcc.gnu.org/g:94ace2557836a6eecb23475e5640c8c4a5407902

commit r15-11395-g94ace2557836a6eecb23475e5640c8c4a5407902
Author: Alexandre Oliva <[email protected]>
Date:   Sat Jan 31 01:52:10 2026 -0300

    testsuite: arm: crypto-vsha1*_u32 tests got late-combine improvements
    
    The late-combine pass enabled some of the vdup.32 instructions
    expected in crypto-vsha1*_u32 tests to use d registers, so accept them
    as well.
    
    While at that, drop the excess + after ] in d register matches in
    vmov.32 instructions.
    
    for  gcc/testsuite/ChangeLog
    
            * gcc.target/arm/crypto-vsha1cq_u32.c: Accept d regs in
            vdup.32.  Drop extraneous + after ] in vmov.32 pattern.
            * gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
            * gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
            * gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
    
    (cherry picked from commit c035985fd611dfb2e43b31ce64faf562f3804c49)

Diff:
---
 gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c | 4 ++--
 gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c  | 4 ++--
 gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c | 4 ++--
 gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
index 0cadd19c4dcc..6a64b61299bf 100644
--- a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
@@ -31,5 +31,5 @@ uint32_t foo (void)
 TEST_SHA1C_VEC_SELECT (GET_LANE)
 
 /* { dg-final { scan-assembler-times {sha1c.32\tq[0-9]+, q[0-9]+} 5 } } */
-/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, r[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]+} 3 } } */
+/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */
+/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
index 33af705c59e3..accf83e88c43 100644
--- a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
@@ -27,5 +27,5 @@ uint32_t foo (void)
 TEST_SHA1H_VEC_SELECT (GET_LANE)
 
 /* { dg-final { scan-assembler-times {sha1h.32\tq[0-9]+, q[0-9]+} 5 } } */
-/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, r[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]+} 3 } } */
+/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */
+/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
index bdd1c4f33159..9d6aa45a0674 100644
--- a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
@@ -31,5 +31,5 @@ uint32_t foo (void)
 TEST_SHA1M_VEC_SELECT (GET_LANE)
 
 /* { dg-final { scan-assembler-times {sha1m.32\tq[0-9]+, q[0-9]+} 5 } } */
-/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, r[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]+} 3 } } */
+/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */
+/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
index d48a07c6fa4e..5fbcad2d2095 100644
--- a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
@@ -31,5 +31,5 @@ uint32_t foo (void)
 TEST_SHA1P_VEC_SELECT (GET_LANE)
 
 /* { dg-final { scan-assembler-times {sha1p.32\tq[0-9]+, q[0-9]+} 5 } } */
-/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, r[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]+} 3 } } */
+/* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 } } */
+/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */