[gcc r17-2593] RISC-V: Add test cases for vfwcvt.f.xu.v reg overlap overlap
Pan Li via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
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https://gcc.gnu.org/g:0eb5dc76092a6e85738f323195d65a4731cec180 commit r17-2593-g0eb5dc76092a6e85738f323195d65a4731cec180 Author: Pan Li <[email protected]> Date: Mon Jul 20 13:38:42 2026 +0800 RISC-V: Add test cases for vfwcvt.f.xu.v reg overlap overlap Add test cases for vfwcvt.f.xu.v register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c | 17 ++++++++++++ .../autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c | 31 ++++++++++++++++++++++ .../autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c | 17 ++++++++++++ .../autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c | 17 ++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c | 31 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c | 31 ++++++++++++++++++++++ 15 files changed, 339 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c new file mode 100644 index 000000000000..d9a31c3fe48e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16m1_t, + vfloat32m2_t, + __riscv_vle16_v_u16m1, + __riscv_vfwcvt_f_xu_v_f32m2, + __riscv_vse32_v_f32m2, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c new file mode 100644 index 000000000000..fed4ff1fbd5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m2, + vuint16m2_t, + vfloat32m4_t, + __riscv_vle16_v_u16m2, + __riscv_vfwcvt_f_xu_v_f32m4, + __riscv_vse32_v_f32m4, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c new file mode 100644 index 000000000000..442a0f0d66b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m4, + vuint16m4_t, + vfloat32m8_t, + __riscv_vle16_v_u16m4, + __riscv_vfwcvt_f_xu_v_f32m8, + __riscv_vse32_v_f32m8, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c new file mode 100644 index 000000000000..28acac0ed4b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf2_t, + vfloat32m1_t, + __riscv_vle16_v_u16mf2, + __riscv_vfwcvt_f_xu_v_f32m1, + __riscv_vse32_v_f32m1, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c new file mode 100644 index 000000000000..303eb6a4cb6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf4_t, + vfloat32mf2_t, + __riscv_vle16_v_u16mf4, + __riscv_vfwcvt_f_xu_v_f32mf2, + __riscv_vse32_v_f32mf2, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c new file mode 100644 index 000000000000..24b162695745 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m1, + vuint32m1_t, + vfloat64m2_t, + __riscv_vle32_v_u32m1, + __riscv_vfwcvt_f_xu_v_f64m2, + __riscv_vse64_v_f64m2, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c new file mode 100644 index 000000000000..df4d3c185b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m2, + vuint32m2_t, + vfloat64m4_t, + __riscv_vle32_v_u32m2, + __riscv_vfwcvt_f_xu_v_f64m4, + __riscv_vse64_v_f64m4, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c new file mode 100644 index 000000000000..6095771111c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m4, + vuint32m4_t, + vfloat64m8_t, + __riscv_vle32_v_u32m4, + __riscv_vfwcvt_f_xu_v_f64m8, + __riscv_vse64_v_f64m8, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c new file mode 100644 index 000000000000..6624043a8ec3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e32m1, + vuint32mf2_t, + vfloat64m1_t, + __riscv_vle32_v_u32mf2, + __riscv_vfwcvt_f_xu_v_f64m1, + __riscv_vse64_v_f64m1, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c new file mode 100644 index 000000000000..8d5e9063345a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8m1_t, + vfloat16m2_t, + __riscv_vle8_v_u8m1, + __riscv_vfwcvt_f_xu_v_f16m2, + __riscv_vse16_v_f16m2, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c new file mode 100644 index 000000000000..2697c28066c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m2, + vuint8m2_t, + vfloat16m4_t, + __riscv_vle8_v_u8m2, + __riscv_vfwcvt_f_xu_v_f16m4, + __riscv_vse16_v_f16m4, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c new file mode 100644 index 000000000000..05930826fba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m4, + vuint8m4_t, + vfloat16m8_t, + __riscv_vle8_v_u8m4, + __riscv_vfwcvt_f_xu_v_f16m8, + __riscv_vse16_v_f16m8, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.xu\.v\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c new file mode 100644 index 000000000000..98a9ea5fcc65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf2_t, + vfloat16m1_t, + __riscv_vle8_v_u8mf2, + __riscv_vfwcvt_f_xu_v_f16m1, + __riscv_vse16_v_f16m1, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c new file mode 100644 index 000000000000..60e5ca978bb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf4_t, + vfloat16mf2_t, + __riscv_vle8_v_u8mf4, + __riscv_vfwcvt_f_xu_v_f16mf2, + __riscv_vse16_v_f16mf2, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c new file mode 100644 index 000000000000..dee8a18c697f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf8_t, + vfloat16mf4_t, + __riscv_vle8_v_u8mf8, + __riscv_vfwcvt_f_xu_v_f16mf4, + __riscv_vse16_v_f16mf4, + vfwcvt_f_xu, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v2,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v4,v5} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v6,v7} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v8,v9} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v10,v11} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v12,v13} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v14,v15} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v16,v17} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v18,v19} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v20,v21} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v22,v23} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v24,v25} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v26,v27} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v28,v29} } } */ +/* { dg-final { scan-assembler-not {vfwcvt\.f\.xu\.v\s+v30,v31} } } */