[gcc r17-2684] target/126328 - [x86] insn_cost of *sse3_h{add, sub}v2df3[_low]

https://gcc.gnu.org/g:d20adcae36e31cb96a9869566a243e3d6f21ab8d

commit r17-2684-gd20adcae36e31cb96a9869566a243e3d6f21ab8d
Author: Richard Biener <[email protected]>
Date:   Tue Jul 21 15:10:24 2026 +0200

    target/126328 - [x86] insn_cost of *sse3_h{add,sub}v2df3[_low]
    
    I run into issues with gcc.target/i386/pr54400.c when SLP vectorizing
    a horizontal reduction of a V2DF vector.  The following plugs the
    remaining hole in costing which prevents combine from doing its work
    to recover the single hadd instruction for { p[0] + p[1], q[0] + q[1] }
    The patch avoids the pattern cost special-casing of vec_concat
    by costing the insn based on a new cost_special attribute which I placed
    on all of the haddsub patterns.
    
            PR target/126328
            PR target/126383
            * config/i386/i386.md (cost_special): New attribute.
            * config/i386/sse.md (avx_h<insn>v4df3): Add cost_special
            attribute with value haddsub.
            (*sse3_haddv2df3): Likewise.
            (sse3_hsubv2df3): Likewise.
            (*sse3_haddv2df3_low): Likewise.
            (*sse3_hsubv2df3_low): Likewise.
            (avx_h<insn>v8sf3): Likewise.
            (sse3_h<insn>v4sf3): Likewise.
            * config/i386/i386.cc (ix86_insn_cost): Cost insns with
            the cost_special attribute value of haddsub like an add.

Diff:
---
 gcc/config/i386/i386.cc | 7 +++++++
 gcc/config/i386/i386.md | 4 ++++
 gcc/config/i386/sse.md  | 7 +++++++
 3 files changed, 18 insertions(+)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 56a90333cfcb..5154025b007e 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -22714,6 +22714,13 @@ ix86_insn_cost (rtx_insn *insn, bool speed)
 					       : COSTS_N_INSNS (3) + 1;
 	}
     }
+  /* Cost *h{add,sub}<mode>[_low] directly as pattern cost for the
+     variants with outer vec_concat are artificially low.  */
+  if (INSN_CODE (insn) >= 0
+      && get_attr_cost_special (insn) == COST_SPECIAL_HADDSUB)
+    return insn_cost + ix86_vec_cost (GET_MODE (pat),
+				      (speed ? ix86_tune_cost
+				       : &ix86_size_cost)->addss);
 
   return insn_cost + pattern_cost (pat, speed);
 }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index fbaf28017bbb..f762b2ccea2d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1032,6 +1032,10 @@
 ;; Define attribute to mark the insn has nf variant.
 (define_attr "has_nf" "0,1" (const_string "0"))
 
+;; Define attribute for insns whose computed pattern cost needs a
+;; special-case override (see ix86_insn_cost).
+(define_attr "cost_special" "haddsub,none" (const_string "none"))
+
 ;; Describe a user's asm statement.
 (define_asm_attributes
   [(set_attr "length" "128")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a3fa2ec5f8f3..38cdf607935d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3772,6 +3772,7 @@
    (set_attr "c86_attr" "hplus")
    (set_attr "addr" "gpr16")
    (set_attr "prefix" "vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V4DF")])
 
 (define_expand "sse3_haddv2df3"
@@ -3817,6 +3818,7 @@
    (set_attr "type" "sseadd")
    (set_attr "c86_attr" "hplus")
    (set_attr "prefix" "orig,vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V2DF")])
 
 (define_insn "sse3_hsubv2df3"
@@ -3841,6 +3843,7 @@
    (set_attr "c86_attr" "hplus")
    (set_attr "addr" "*,gpr16")
    (set_attr "prefix" "orig,vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V2DF")])
 
 (define_insn "*sse3_haddv2df3_low"
@@ -3861,6 +3864,7 @@
    (set_attr "type" "sseadd1")
    (set_attr "c86_attr" "hplus")
    (set_attr "prefix" "orig,vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V2DF")])
 
 (define_insn "*sse3_hsubv2df3_low"
@@ -3880,6 +3884,7 @@
    (set_attr "type" "sseadd1")
    (set_attr "c86_attr" "hplus")
    (set_attr "prefix" "orig,vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V2DF")])
 
 (define_insn "avx_h<insn>v8sf3"
@@ -3925,6 +3930,7 @@
    (set_attr "c86_attr" "hplus")
    (set_attr "addr" "gpr16")
    (set_attr "prefix" "vex")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V8SF")])
 
 (define_insn "sse3_h<insn>v4sf3"
@@ -3959,6 +3965,7 @@
    (set_attr "atom_unit" "complex")
    (set_attr "prefix" "orig,vex")
    (set_attr "prefix_rep" "1,*")
+   (set_attr "cost_special" "haddsub")
    (set_attr "mode" "V4SF")])
 
 (define_mode_iterator REDUC_SSE_PLUS_MODE