[gcc r16-9396] rs6000: Add DMF-specific XO move pattern

https://gcc.gnu.org/g:118f964b779497deff9e83fcb9a685b6d1f4dce4

commit r16-9396-g118f964b779497deff9e83fcb9a685b6d1f4dce4
Author: Vijay Shankar <[email protected]>
Date:   Mon Jul 20 03:04:54 2026 -0500

    rs6000: Add DMF-specific XO move pattern
    
    Split the movxo pattern into DMF and non-DMF variants.
    
    Use DMF move instructions (dmxxinstdmr512, dmmr, and dmxxextfdmr512)
    for accumulator/DMR moves while retaining the existing split for
    non-DMR operands.
    
    2026-07-15  Vijay Shankar  <[email protected]>
    
    gcc/ChangeLog:
            * config/rs6000/mma.md (*movxo): renamed to movxo_nodmf
            (*movxo_nodmf): updated contraint to use wD and add !TARGET_DMF
            (*movxo_dmf): New pattern to handle dmf insert/extract from vsx
    
    (cherry picked from commit 4ee8fd77c38e84906be22bea066086b464985f68)

Diff:
---
 gcc/config/rs6000/mma.md | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 9becb9be0697..85caa19ee10b 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -344,10 +344,10 @@
     gcc_assert (false);
 })
 
-(define_insn_and_split "*movxo"
-  [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
-	(match_operand:XO 1 "input_operand" "ZwO,d,d"))]
-  "TARGET_MMA
+(define_insn_and_split "*movxo_nodmf"
+  [(set (match_operand:XO 0 "nonimmediate_operand" "=wD,ZwO,wD")
+	(match_operand:XO 1 "input_operand" "ZwO,wD,wD"))]
+  "TARGET_MMA && !TARGET_DMF
    && (gpc_reg_operand (operands[0], XOmode)
        || gpc_reg_operand (operands[1], XOmode))"
   "@
@@ -364,6 +364,31 @@
    (set_attr "length" "*,*,16")
    (set_attr "max_prefixed_insns" "2,2,*")])
 
+(define_insn_and_split "*movxo_dmf"
+  [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,ZwO,wa,wD,wD,wa")
+        (match_operand:XO 1 "input_operand"        "ZwO,wa, wa,wa,wD,wD"))]
+  "TARGET_DMF
+   && (gpc_reg_operand (operands[0], XOmode)
+       || gpc_reg_operand (operands[1], XOmode))"
+  "@
+   #
+   #
+   #
+   dmxxinstdmr512 %0,%x1,%W1,0
+   dmmr %0,%1
+   dmxxextfdmr512 %x0,%W0,%1,0"
+  "&& reload_completed
+   && !dmr_register_operand (operands[0], XOmode)
+   && !dmr_register_operand (operands[1], XOmode)"
+  [(const_int 0)]
+{
+  rs6000_split_multireg_move (operands[0], operands[1]);
+  DONE;
+}
+  [(set_attr "type" "vecload,vecstore,veclogical,dmf,dmf,dmf")
+   (set_attr "length" "*,*,16,*,*,*")
+   (set_attr "max_prefixed_insns" "2,2,*,*,*,*")])
+
 (define_expand "vsx_assemble_pair"
   [(match_operand:OO 0 "vsx_register_operand")
    (match_operand:V16QI 1 "mma_assemble_input_operand")