[gcc r17-2755] aarch64: Add support for sve2p3 and sme2p3 conversion intrinsics
Richard Ball via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:7695a61179f48ff9e5cfb953bbf31309c5500a1a commit r17-2755-g7695a61179f48ff9e5cfb953bbf31309c5500a1a Author: Richard Ball <[email protected]> Date: Tue Jul 28 15:53:36 2026 +0100 aarch64: Add support for sve2p3 and sme2p3 conversion intrinsics This patch adds support for new intrinsics which make use of the conversion instructions introduced in SVE2p3/SME2p3. gcc/ChangeLog: * config/aarch64/aarch64-acle-builtins.h (TYPES_cvtzn): New function types. (TYPES_cvttb): Likewise. (cvtzn): Likewise. (cvttb): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.cc (class svcvtt_impl): New function impl. (class svcvtb_impl): Likewise. (FUNCTION): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def (svcvtn): New function. (svcvtt): Likewise. (svcvtb): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.h: Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_sve2_scvtfb<mode>): New pattern. (@aarch64_sve2_scvtflt<mode>): Likewise. (@aarch64_sve2_ucvtfb<mode>): Likewise. (@aarch64_sve2_ucvtflt<mode>): Likewise. (@aarch64_sve2_fcvtzsn<mode>): Likewise. (@aarch64_sve2_fcvtzun<mode>): Likewise. * config/aarch64/iterators.md (b): Ventype changes. (VNx16HF): Likewise. (VNx16QI): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c: New test. * gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c: New test. Diff: --- gcc/config/aarch64/aarch64-acle-builtins.h | 18 ++++++ gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 38 ++++++++++- gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 3 + gcc/config/aarch64/aarch64-sve-builtins-sve2.h | 2 + gcc/config/aarch64/aarch64-sve2.md | 73 ++++++++++++++++++++++ gcc/config/aarch64/iterators.md | 16 ++++- .../gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c | 24 +++++++ .../gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtb_f32_s16.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtb_f32_u16.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtb_f64_s32.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtb_f64_u32.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c | 53 ++++++++++++++++ .../aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c | 53 ++++++++++++++++ .../aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c | 53 ++++++++++++++++ .../aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c | 53 ++++++++++++++++ .../aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c | 53 ++++++++++++++++ .../aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c | 53 ++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c | 24 +++++++ .../gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtt_f32_s16.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtt_f32_u16.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtt_f64_s32.c | 24 +++++++ .../aarch64/sme2/acle-asm/cvtt_f64_u32.c | 24 +++++++ 24 files changed, 754 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-acle-builtins.h b/gcc/config/aarch64/aarch64-acle-builtins.h index bf495bd74a0d..17b3da74858d 100644 --- a/gcc/config/aarch64/aarch64-acle-builtins.h +++ b/gcc/config/aarch64/aarch64-acle-builtins.h @@ -1524,6 +1524,22 @@ function_expander::result_mode () const #define TYPES_cvtnx_mf8(S, D, T) \ D (mf8, f32) +#define TYPES_cvtzn(S, D, T) \ + D (s8, f16), \ + D (u8, f16), \ + D (s16, f32), \ + D (u16, f32), \ + D (s32, f64), \ + D (u32, f64) + +#define TYPES_cvttb(S, D, T) \ + D (f16, s8), \ + D (f16, u8), \ + D (f32, s16), \ + D (f32, u16), \ + D (f64, s32), \ + D (f64, u32) + /* { _s32 _s64 } x { _b8 _b16 _b32 _b64 } { _u32 _u64 }. */ #define TYPES_inc_dec_n1(D, A) \ @@ -2017,6 +2033,8 @@ DEF_SVE_TYPES_ARRAY (cvt_narrow); DEF_SVE_TYPES_ARRAY (cvt_s_s); DEF_SVE_TYPES_ARRAY (cvtn_mf8); DEF_SVE_TYPES_ARRAY (cvtnx_mf8); +DEF_SVE_TYPES_ARRAY (cvtzn); +DEF_SVE_TYPES_ARRAY (cvttb); DEF_SVE_TYPES_ARRAY (inc_dec_n); DEF_SVE_TYPES_ARRAY (qcvt_x2); DEF_SVE_TYPES_ARRAY (qcvt_x4); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index e969953ab1d6..a06475529f91 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -245,8 +245,42 @@ public: insn_code icode; if (e.fpm_mode == FPM_set) icode = code_for_aarch64_sve2_fp8_cvtn (GET_MODE (e.args[0])); - else + else if (e.type_suffix (0).float_p) icode = code_for_aarch64_sve_cvtn (e.result_mode ()); + else if (e.type_suffix (0).unsigned_p) + icode = code_for_aarch64_sve2_fcvtzun (e.result_mode ()); + else + icode = code_for_aarch64_sve2_fcvtzsn (e.result_mode ()); + return e.use_exact_insn (icode); + } +}; + +class svcvtt_impl : public function_base +{ +public: + rtx + expand (function_expander &e) const override + { + insn_code icode; + if (e.type_suffix (1).unsigned_p) + icode = code_for_aarch64_sve2_ucvtflt (e.result_mode ()); + else + icode = code_for_aarch64_sve2_scvtflt (e.result_mode ()); + return e.use_exact_insn (icode); + } +}; + +class svcvtb_impl : public function_base +{ +public: + rtx + expand (function_expander &e) const override + { + insn_code icode; + if (e.type_suffix (1).unsigned_p) + icode = code_for_aarch64_sve2_ucvtfb (e.result_mode ()); + else + icode = code_for_aarch64_sve2_scvtfb (e.result_mode ()); return e.use_exact_insn (icode); } }; @@ -1072,6 +1106,8 @@ FUNCTION (svcvtn, svcvtn_impl,) FUNCTION (svcvtnb, fixed_insn_function, (CODE_FOR_aarch64_sve2_fp8_cvtnbvnx16qi)) FUNCTION (svcvtx, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTX)) FUNCTION (svcvtxnt, NARROWING_TOP_CONVERT1 (aarch64_sve2_cvtxnt),) +FUNCTION (svcvtt, svcvtt_impl,) +FUNCTION (svcvtb, svcvtb_impl,) FUNCTION (svdup_laneq, svdup_laneq_impl,) FUNCTION (sveor3, CODE_FOR_MODE0 (aarch64_sve2_eor3),) FUNCTION (sveorbt, unspec_based_function, (UNSPEC_EORBT, UNSPEC_EORBT, -1)) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 62474935b49c..a977b2c1c1a5 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -468,6 +468,9 @@ DEF_SVE_FUNCTION_GS_FPM (svmmla, mmla, s_float_mf8, none, none, set) #define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3, AARCH64_FL_SME2p3) DEF_SVE_FUNCTION (svdot, ternary_qq_opt_n_or_011, s_narrow_su, none) DEF_SVE_FUNCTION (svdot_lane, ternary_qq_or_011_lane, s_narrow_su, none) +DEF_SVE_FUNCTION_GS (svcvtn, unary_convertxn, cvtzn, x2, none) +DEF_SVE_FUNCTION (svcvtt, unary_convert, cvttb, none) +DEF_SVE_FUNCTION (svcvtb, unary_convert, cvttb, none) #undef REQUIRED_EXTENSIONS #define REQUIRED_EXTENSIONS nonstreaming_sve (AARCH64_FL_SVE_F16F32MM) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h index 168c4b69e336..4bf8f21776a0 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h @@ -70,6 +70,8 @@ namespace aarch64_acle extern const function_base *const svcvtlt1; extern const function_base *const svcvtlt2; extern const function_base *const svcvtn; + extern const function_base *const svcvtt; + extern const function_base *const svcvtb; extern const function_base *const svcvtnb; extern const function_base *const svcvtnt; extern const function_base *const svcvtx; diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 873d47368294..a8bee6b6dc7c 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -105,6 +105,7 @@ ;; ;; == Conversions ;; ---- [FP<-FP] Widening conversions +;; ---- [FP<-INT] Widening conversions ;; ---- [FP<-FP] Narrowing conversions ;; ---- [FP<-FP] Multi-vector widening conversions ;; ---- [FP<-FP] Multi-vector narrowing conversions @@ -3668,6 +3669,56 @@ [(set_attr "sve_type" "sve_fp_cvt")] ) +;; ------------------------------------------------------------------------- +;; ---- [FP<-INT] Widening conversions +;; ------------------------------------------------------------------------- +;; Includes: +;; - SCVTF (SME_2p3) +;; - SCVTFLT (SME_2p3) +;; - UCVTF (SME_2p3) +;; - UCVTFLT (SME_2p3) +;; ------------------------------------------------------------------------- + +(define_insn "@aarch64_sve2_scvtfb<mode>" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + (unspec:SVE_FULL_F + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")] + UNSPEC_SCVTFB))] + "TARGET_SVE2p3_OR_SME2p3" + "scvtf\t%0.<Vetype>, %1.<Ventype>" + [(set_attr "sve_type" "sve_fp_cvt")] +) + +(define_insn "@aarch64_sve2_scvtflt<mode>" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + (unspec:SVE_FULL_F + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")] + UNSPEC_SCVTFLT))] + "TARGET_SVE2p3_OR_SME2p3" + "scvtflt\t%0.<Vetype>, %1.<Ventype>" + [(set_attr "sve_type" "sve_fp_cvt")] +) + +(define_insn "@aarch64_sve2_ucvtfb<mode>" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + (unspec:SVE_FULL_F + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")] + UNSPEC_UCVTFB))] + "TARGET_SVE2p3_OR_SME2p3" + "ucvtf\t%0.<Vetype>, %1.<Ventype>" + [(set_attr "sve_type" "sve_fp_cvt")] +) + +(define_insn "@aarch64_sve2_ucvtflt<mode>" + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + (unspec:SVE_FULL_F + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")] + UNSPEC_UCVTFLT))] + "TARGET_SVE2p3_OR_SME2p3" + "ucvtflt\t%0.<Vetype>, %1.<Ventype>" + [(set_attr "sve_type" "sve_fp_cvt")] +) + ;; ------------------------------------------------------------------------- ;; ---- [FP<-FP] Narrowing conversions ;; ------------------------------------------------------------------------- @@ -3935,6 +3986,8 @@ ;; Includes the multi-register forms of: ;; - FCVTZS (SME2) ;; - FCVTZU (SME2) +;; - FCVTZSN (SME2p3) +;; - FCVTZUN (SME2p3) ;; ------------------------------------------------------------------------- (define_insn "<optab><mode><v_int_equiv>2" @@ -3946,6 +3999,26 @@ [(set_attr "sve_type" "sve_fp_cvt")] ) +(define_insn "@aarch64_sve2_fcvtzsn<mode>" + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") + (unspec:SVE_FULL_BHSI + [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")] + UNSPEC_FCVTZSN))] + "TARGET_SVE2p3_OR_SME2p3" + "fcvtzsn\t%0.<Vetype>, %1" + [(set_attr "sve_type" "sve_fp_cvt")] +) + +(define_insn "@aarch64_sve2_fcvtzun<mode>" + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w") + (unspec:SVE_FULL_BHSI + [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")] + UNSPEC_FCVTZUN))] + "TARGET_SVE2p3_OR_SME2p3" + "fcvtzun\t%0.<Vetype>, %1" + [(set_attr "sve_type" "sve_fp_cvt")] +) + ;; ========================================================================= ;; == Other arithmetic ;; ========================================================================= diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 5dfb27449703..0d319751430d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1123,6 +1123,12 @@ UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md. UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md. UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md. + UNSPEC_FCVTZSN ; Used in aarch64-sve2.md. + UNSPEC_FCVTZUN ; Used in aarch64-sve2.md. + UNSPEC_SCVTFB ; Used in aarch64-sve2.md. + UNSPEC_SCVTFLT ; Used in aarch64-sve2.md. + UNSPEC_UCVTFB ; Used in aarch64-sve2.md. + UNSPEC_UCVTFLT ; Used in aarch64-sve2.md. UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md. UNSPEC_DOT_FP8 ; Used in aarch64-sve2.md. UNSPEC_DOT_LANE_FP8 ; Used in aarch64-sve2.md. @@ -2278,7 +2284,7 @@ (V8HI "4s") (V4SI "2d")]) ;; SVE vector after narrowing. -(define_mode_attr Ventype [(VNx8HI "b") +(define_mode_attr Ventype [(VNx8HI "b") (VNx8HF "b") (VNx4SI "h") (VNx4SF "h") (VNx2DI "s") (VNx2DF "s") (VNx8SI "h") (VNx16SI "b") @@ -2909,6 +2915,14 @@ (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]") ]) +(define_mode_attr FCVTZN_SRC [(VNx16QI "VNx16HF") + (VNx8HI "VNx8SF") + (VNx4SI "VNx4DF")]) + +(define_mode_attr CVTTB_SRC [(VNx8HF "VNx16QI") + (VNx4SF "VNx8HI") + (VNx2DF "VNx4SI")]) + (define_mode_attr za16_offset_range [(VNx16QI "0_to_14_step_2") (VNx32QI "0_to_6_step_2") (VNx64QI "0_to_6_step_2")]) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c new file mode 100644 index 000000000000..1d8e708938e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** scvtf z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat16_t, svint8_t, + z0 = svcvtb_f16_s8 (z4), + z0 = svcvtb_f16 (z4)) + +/* +** cvtb_tied: +** scvtf z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svint8_t, + z0_res = svcvtb_f16_s8 (z0), + z0_res = svcvtb_f16 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c new file mode 100644 index 000000000000..017909d28a28 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** ucvtf z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat16_t, svuint8_t, + z0 = svcvtb_f16_u8 (z4), + z0 = svcvtb_f16 (z4)) + +/* +** cvtb_tied: +** ucvtf z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svuint8_t, + z0_res = svcvtb_f16_u8 (z0), + z0_res = svcvtb_f16 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c new file mode 100644 index 000000000000..64d4a048ff82 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** scvtf z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat32_t, svint16_t, + z0 = svcvtb_f32_s16 (z4), + z0 = svcvtb_f32 (z4)) + +/* +** cvtb_tied: +** scvtf z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svint16_t, + z0_res = svcvtb_f32_s16 (z0), + z0_res = svcvtb_f32 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c new file mode 100644 index 000000000000..c2817ee80032 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** ucvtf z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat32_t, svuint16_t, + z0 = svcvtb_f32_u16 (z4), + z0 = svcvtb_f32 (z4)) + +/* +** cvtb_tied: +** ucvtf z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svuint16_t, + z0_res = svcvtb_f32_u16 (z0), + z0_res = svcvtb_f32 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c new file mode 100644 index 000000000000..96e20742f8f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** scvtf z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat64_t, svint32_t, + z0 = svcvtb_f64_s32 (z4), + z0 = svcvtb_f64 (z4)) + +/* +** cvtb_tied: +** scvtf z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svint32_t, + z0_res = svcvtb_f64_s32 (z0), + z0_res = svcvtb_f64 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c new file mode 100644 index 000000000000..4fb145ff3472 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtb_untied: +** ucvtf z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (cvtb_untied, svfloat64_t, svuint32_t, + z0 = svcvtb_f64_u32 (z4), + z0 = svcvtb_f64 (z4)) + +/* +** cvtb_tied: +** ucvtf z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svuint32_t, + z0_res = svcvtb_f64_u32 (z0), + z0_res = svcvtb_f64 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c new file mode 100644 index 000000000000..3e951655eb34 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzsn z0\.h, {z0\.s - z1\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat32x2_t, svint16_t, + z0_res = svcvtn_s16_f32_x2 (z0), + z0_res = svcvtn_s16 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzsn z0\.h, {z6\.s - z7\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat32x2_t, svint16_t, + z0_res = svcvtn_s16_f32_x2 (z6), + z0_res = svcvtn_s16 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzsn z0\.h, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat32x2_t, svint16_t, + z0_res = svcvtn_s16_f32_x2 (z29), + z0_res = svcvtn_s16 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzsn z5\.h, {z0\.s - z1\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat32x2_t, svint16_t, + z5 = svcvtn_s16_f32_x2 (z0), + z5 = svcvtn_s16 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzsn z22\.h, {z16\.s - z17\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat32x2_t, svint16_t, + z22 = svcvtn_s16_f32_x2 (z16), + z22 = svcvtn_s16 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c new file mode 100644 index 000000000000..8d29ac79d660 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzsn z0\.s, {z0\.d - z1\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat64x2_t, svint32_t, + z0_res = svcvtn_s32_f64_x2 (z0), + z0_res = svcvtn_s32 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzsn z0\.s, {z6\.d - z7\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat64x2_t, svint32_t, + z0_res = svcvtn_s32_f64_x2 (z6), + z0_res = svcvtn_s32 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzsn z0\.s, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat64x2_t, svint32_t, + z0_res = svcvtn_s32_f64_x2 (z29), + z0_res = svcvtn_s32 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzsn z5\.s, {z0\.d - z1\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat64x2_t, svint32_t, + z5 = svcvtn_s32_f64_x2 (z0), + z5 = svcvtn_s32 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzsn z22\.s, {z16\.d - z17\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat64x2_t, svint32_t, + z22 = svcvtn_s32_f64_x2 (z16), + z22 = svcvtn_s32 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c new file mode 100644 index 000000000000..8fcea19f00d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzsn z0\.b, {z0\.h - z1\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat16x2_t, svint8_t, + z0_res = svcvtn_s8_f16_x2 (z0), + z0_res = svcvtn_s8 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzsn z0\.b, {z6\.h - z7\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat16x2_t, svint8_t, + z0_res = svcvtn_s8_f16_x2 (z6), + z0_res = svcvtn_s8 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzsn z0\.b, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat16x2_t, svint8_t, + z0_res = svcvtn_s8_f16_x2 (z29), + z0_res = svcvtn_s8 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzsn z5\.b, {z0\.h - z1\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat16x2_t, svint8_t, + z5 = svcvtn_s8_f16_x2 (z0), + z5 = svcvtn_s8 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzsn z22\.b, {z16\.h - z17\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat16x2_t, svint8_t, + z22 = svcvtn_s8_f16_x2 (z16), + z22 = svcvtn_s8 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c new file mode 100644 index 000000000000..c70101e0f195 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzun z0\.h, {z0\.s - z1\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat32x2_t, svuint16_t, + z0_res = svcvtn_u16_f32_x2 (z0), + z0_res = svcvtn_u16 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzun z0\.h, {z6\.s - z7\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat32x2_t, svuint16_t, + z0_res = svcvtn_u16_f32_x2 (z6), + z0_res = svcvtn_u16 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzun z0\.h, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat32x2_t, svuint16_t, + z0_res = svcvtn_u16_f32_x2 (z29), + z0_res = svcvtn_u16 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzun z5\.h, {z0\.s - z1\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat32x2_t, svuint16_t, + z5 = svcvtn_u16_f32_x2 (z0), + z5 = svcvtn_u16 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzun z22\.h, {z16\.s - z17\.s} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat32x2_t, svuint16_t, + z22 = svcvtn_u16_f32_x2 (z16), + z22 = svcvtn_u16 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c new file mode 100644 index 000000000000..155c9f0bc7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzun z0\.s, {z0\.d - z1\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat64x2_t, svuint32_t, + z0_res = svcvtn_u32_f64_x2 (z0), + z0_res = svcvtn_u32 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzun z0\.s, {z6\.d - z7\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat64x2_t, svuint32_t, + z0_res = svcvtn_u32_f64_x2 (z6), + z0_res = svcvtn_u32 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzun z0\.s, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat64x2_t, svuint32_t, + z0_res = svcvtn_u32_f64_x2 (z29), + z0_res = svcvtn_u32 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzun z5\.s, {z0\.d - z1\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat64x2_t, svuint32_t, + z5 = svcvtn_u32_f64_x2 (z0), + z5 = svcvtn_u32 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzun z22\.s, {z16\.d - z17\.d} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat64x2_t, svuint32_t, + z22 = svcvtn_u32_f64_x2 (z16), + z22 = svcvtn_u32 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c new file mode 100644 index 000000000000..31c0a584f2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c @@ -0,0 +1,53 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtn_z0_z0: +** fcvtzun z0\.b, {z0\.h - z1\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z0, svfloat16x2_t, svuint8_t, + z0_res = svcvtn_u8_f16_x2 (z0), + z0_res = svcvtn_u8 (z0)) + +/* +** cvtn_z0_z6: +** fcvtzun z0\.b, {z6\.h - z7\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z6, svfloat16x2_t, svuint8_t, + z0_res = svcvtn_u8_f16_x2 (z6), + z0_res = svcvtn_u8 (z6)) + +/* +** cvtn_z0_z29: +** mov [^\n]+ +** mov [^\n]+ +** fcvtzun z0\.b, [^\n]+ +** ret +*/ +TEST_X2_NARROW (cvtn_z0_z29, svfloat16x2_t, svuint8_t, + z0_res = svcvtn_u8_f16_x2 (z29), + z0_res = svcvtn_u8 (z29)) + +/* +** cvtn_z5_z0: +** fcvtzun z5\.b, {z0\.h - z1\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z5_z0, svfloat16x2_t, svuint8_t, + z5 = svcvtn_u8_f16_x2 (z0), + z5 = svcvtn_u8 (z0)) + +/* +** cvtn_z22_z16: +** fcvtzun z22\.b, {z16\.h - z17\.h} +** ret +*/ +TEST_X2_NARROW (cvtn_z22_z16, svfloat16x2_t, svuint8_t, + z22 = svcvtn_u8_f16_x2 (z16), + z22 = svcvtn_u8 (z16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c new file mode 100644 index 000000000000..7cd6ea16180e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** scvtflt z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat16_t, svint8_t, + z0 = svcvtt_f16_s8 (z4), + z0 = svcvtt_f16 (z4)) + +/* +** cvtt_tied: +** scvtflt z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svint8_t, + z0_res = svcvtt_f16_s8 (z0), + z0_res = svcvtt_f16 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c new file mode 100644 index 000000000000..c678169010fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** ucvtflt z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat16_t, svuint8_t, + z0 = svcvtt_f16_u8 (z4), + z0 = svcvtt_f16 (z4)) + +/* +** cvtt_tied: +** ucvtflt z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svuint8_t, + z0_res = svcvtt_f16_u8 (z0), + z0_res = svcvtt_f16 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c new file mode 100644 index 000000000000..02711748f622 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** scvtflt z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat32_t, svint16_t, + z0 = svcvtt_f32_s16 (z4), + z0 = svcvtt_f32 (z4)) + +/* +** cvtt_tied: +** scvtflt z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svint16_t, + z0_res = svcvtt_f32_s16 (z0), + z0_res = svcvtt_f32 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c new file mode 100644 index 000000000000..3189e239ab46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** ucvtflt z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat32_t, svuint16_t, + z0 = svcvtt_f32_u16 (z4), + z0 = svcvtt_f32 (z4)) + +/* +** cvtt_tied: +** ucvtflt z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svuint16_t, + z0_res = svcvtt_f32_u16 (z0), + z0_res = svcvtt_f32 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c new file mode 100644 index 000000000000..6e4744dfad65 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** scvtflt z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat64_t, svint32_t, + z0 = svcvtt_f64_s32 (z4), + z0 = svcvtt_f64 (z4)) + +/* +** cvtt_tied: +** scvtflt z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svint32_t, + z0_res = svcvtt_f64_s32 (z0), + z0_res = svcvtt_f64 (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c new file mode 100644 index 000000000000..1d097d06bcec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c @@ -0,0 +1,24 @@ +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" +#pragma GCC target "+sme2p3" + +/* +** cvtt_untied: +** ucvtflt z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (cvtt_untied, svfloat64_t, svuint32_t, + z0 = svcvtt_f64_u32 (z4), + z0 = svcvtt_f64 (z4)) + +/* +** cvtt_tied: +** ucvtflt z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svuint32_t, + z0_res = svcvtt_f64_u32 (z0), + z0_res = svcvtt_f64 (z0))