[gcc r17-2808] doc: Spell CPU in uppercase letters

https://gcc.gnu.org/g:a800630087b679ab4658bbaed2b3828d67b19e7e

commit r17-2808-ga800630087b679ab4658bbaed2b3828d67b19e7e
Author: Gerald Pfeifer <[email protected]>
Date:   Thu Jul 30 09:16:30 2026 +0200

    doc: Spell CPU in uppercase letters
    
    gcc:
            * doc/invoke.texi (AArch64 Options): Spell CPU in uppercase
            letters.
            (RS/6000 and PowerPC Options): Ditto.
            (S/390 and zSeries Options): Ditto.
            (SPARC Options): Ditto.

Diff:
---
 gcc/doc/invoke.texi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3d4b3d2bba03..d3de8e88c3b1 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21539,7 +21539,7 @@ This option requires binutils 2.26 or newer.
 Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
 This involves inserting a NOP instruction between memory instructions and
 64-bit integer multiply-accumulate instructions.  This flag will be ignored if
-an architecture or cpu is specified on the command line which does not need the
+an architecture or CPU is specified on the command line which does not need the
 workaround.
 
 @opindex mfix-cortex-a53-843419
@@ -21549,7 +21549,7 @@ workaround.
 Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
 This erratum workaround is made at link time and this will only pass the
 corresponding flag to the linker.  This flag will be ignored if
-an architecture or cpu is specified on the command line which does not need the
+an architecture or CPU is specified on the command line which does not need the
 workaround.
 
 
@@ -21607,7 +21607,7 @@ This option is only applicable when compiling for the base ARMv8.0
 instruction set.  If using a later revision, e.g. @option{-march=armv8.1-a}
 or @option{-march=armv8-a+lse}, the ARMv8.1-Atomics instructions will be
 used directly.  The same applies when using @option{-mcpu=} when the
-selected cpu supports the @samp{lse} feature.
+selected CPU supports the @samp{lse} feature.
 This option is on by default.
 
 @opindex mmax-vectorization
@@ -31802,7 +31802,7 @@ endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC
 architecture machine types, with an appropriate, generic processor
 model assumed for scheduling purposes.
 
-Specifying @samp{native} as cpu type detects and selects the
+Specifying @samp{native} as CPU type detects and selects the
 architecture option that corresponds to the host processor of the
 system performing the compilation.
 @option{-mcpu=native} has no effect if GCC does not recognize the
@@ -33371,7 +33371,7 @@ system representing a certain processor type.  Possible values for
 
 The default is @option{-march=z900}.
 
-Specifying @samp{native} as cpu type can be used to select the best
+Specifying @samp{native} as CPU type can be used to select the best
 architecture option for the host processor.
 @option{-march=native} has no effect if GCC does not recognize the
 processor.
@@ -34333,7 +34333,7 @@ Visual Instruction Set extensions.  The default is @option{-mno-vis}.
 @itemx -mno-vis2
 With @option{-mvis2}, GCC generates code that takes advantage of
 version 2.0 of the UltraSPARC Visual Instruction Set extensions.  The
-default is @option{-mvis2} when targeting a cpu that supports such
+default is @option{-mvis2} when targeting a CPU that supports such
 instructions, such as UltraSPARC-III and later.  Setting @option{-mvis2}
 also sets @option{-mvis}.
 
@@ -34343,7 +34343,7 @@ also sets @option{-mvis}.
 @itemx -mno-vis3
 With @option{-mvis3}, GCC generates code that takes advantage of
 version 3.0 of the UltraSPARC Visual Instruction Set extensions.  The
-default is @option{-mvis3} when targeting a cpu that supports such
+default is @option{-mvis3} when targeting a CPU that supports such
 instructions, such as niagara-3 and later.  Setting @option{-mvis3}
 also sets @option{-mvis2} and @option{-mvis}.
 
@@ -34355,7 +34355,7 @@ With @option{-mvis3b}, GCC generates code that takes advantage of
 version 3.0 of the UltraSPARC Visual Instruction Set extensions, plus
 the additional VIS instructions introduced in the Oracle SPARC
 Architecture 2011. The default is @option{-mvis3b} when targeting
-a cpu that supports such instructions, such as niagara-7 and later.
+a CPU that supports such instructions, such as niagara-7 and later.
 Setting @option{-mvis3b} also sets @option{-mvis3}, @option{-mvis2}
 and @option{-mvis}.
 
@@ -34365,7 +34365,7 @@ and @option{-mvis}.
 @itemx -mno-vis4
 With @option{-mvis4}, GCC generates code that takes advantage of
 version 4.0 of the UltraSPARC Visual Instruction Set extensions.  The
-default is @option{-mvis4} when targeting a cpu that supports such
+default is @option{-mvis4} when targeting a CPU that supports such
 instructions, such as niagara-7 and later.  Setting @option{-mvis4}
 also sets @option{-mvis3b}, @option{-mvis3}, @option{-mvis2} and
 @option{-mvis}.
@@ -34378,7 +34378,7 @@ With @option{-mvis4b}, GCC generates code that takes advantage of
 version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus
 the additional VIS instructions introduced in the Oracle SPARC
 Architecture 2017.  The default is @option{-mvis4b} when targeting a
-cpu that supports such instructions, such as m8 and later.  Setting
+CPU that supports such instructions, such as m8 and later.  Setting
 @option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3b},
 @option{-mvis3}, @option{-mvis2} and @option{-mvis}.