[gcc r17-2810] RISC-V: Add missing bit-field extraction tests

https://gcc.gnu.org/g:437be2f97377104a5cf839a9f9d3662155c02dfe

commit r17-2810-g437be2f97377104a5cf839a9f9d3662155c02dfe
Author: Jin Ma <[email protected]>
Date:   Wed Jul 29 16:00:56 2026 +0800

    RISC-V: Add missing bit-field extraction tests
    
    Add the tests omitted from the original change.
    
    Discussion:
    https://patchwork.sourceware.org/project/gcc/patch/[email protected]/
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/extract-sign-no-scratch.c: New test.
            * gcc.target/riscv/extract-zero-no-scratch.c: New test.

Diff:
---
 .../gcc.target/riscv/extract-sign-no-scratch.c     | 41 ++++++++++++++++++++++
 .../gcc.target/riscv/extract-zero-no-scratch.c     | 41 ++++++++++++++++++++++
 2 files changed, 82 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/extract-sign-no-scratch.c b/gcc/testsuite/gcc.target/riscv/extract-sign-no-scratch.c
new file mode 100644
index 000000000000..9fba99547b3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/extract-sign-no-scratch.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target { ! riscv_abi_e } } } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-Os" "-Oz" "-Og" "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** sign_ext_11_5:
+**	slli	([ast][0-9]+),[ast][0-9]+,48
+**	srai	\1,\1,53
+**	ret
+*/
+long
+sign_ext_11_5 (unsigned long x)
+{
+  return (long) (x << 48) >> 53;
+}
+
+/*
+** sign_ext_16_8:
+**	slli	([ast][0-9]+),[ast][0-9]+,40
+**	srai	\1,\1,48
+**	ret
+*/
+long
+sign_ext_16_8 (unsigned long x)
+{
+  return (long) (x << 40) >> 48;
+}
+
+/*
+** sign_ext_10_20:
+**	slli	([ast][0-9]+),[ast][0-9]+,34
+**	srai	\1,\1,54
+**	ret
+*/
+long
+sign_ext_10_20 (unsigned long x)
+{
+  return (long) (x << 34) >> 54;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/extract-zero-no-scratch.c b/gcc/testsuite/gcc.target/riscv/extract-zero-no-scratch.c
new file mode 100644
index 000000000000..f68c9213760d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/extract-zero-no-scratch.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target { ! riscv_abi_e } } } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-Os" "-Oz" "-Og" "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** zero_ext_20_8:
+**	slli	([ast][0-9]+),[ast][0-9]+,36
+**	srli	\1,\1,44
+**	ret
+*/
+unsigned long
+zero_ext_20_8 (unsigned long x)
+{
+  return (x >> 8) & 0xfffffUL;
+}
+
+/*
+** zero_ext_16_8:
+**	slli	([ast][0-9]+),[ast][0-9]+,40
+**	srli	\1,\1,48
+**	ret
+*/
+unsigned long
+zero_ext_16_8 (unsigned long x)
+{
+  return (x >> 8) & 0xffffUL;
+}
+
+/*
+** zero_ext_13_20:
+**	slli	([ast][0-9]+),[ast][0-9]+,31
+**	srli	\1,\1,51
+**	ret
+*/
+unsigned long
+zero_ext_13_20 (unsigned long x)
+{
+  return (x >> 20) & 0x1fffUL;
+}