[gcc(refs/users/meissner/heads/work255-float)] Add conversions between _Float16 and float/double.
Michael Meissner via Gcc-cvs <[email protected]> Tue, 4 Aug 2026 02:16:49 +0000 (GMT)
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:bda1603e538e9c7c6aa1b59662845af6bb5026c8 commit bda1603e538e9c7c6aa1b59662845af6bb5026c8 Author: Michael Meissner <[email protected]> Date: Mon Aug 3 19:56:49 2026 -0400 Add conversions between _Float16 and float/double. This patch adds support to generate xscvhpdp and xscvdphp on Power9 systems and later, to convert between _Float16 and float scalar values. I have committed all of the patches in my backlog (dense math registers, other -mcpu=future instructions, random bug fixes, support for _Float16 and __bf16, and optimizations for vector logical operations on power10/power11) into the IBM vendor branch: vendors/ibm/gcc-17-future 2026-08-03 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (FP16_HW): New mode iterator. (extendhf<mode>2): Add support converting between HFmode and SFmode/DFmoded if we are on power9 or later. (trunc<mode>hf2): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define __FLOAT16_HW__ if we have hardware support for _Float16. * config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Mark that we use VSX arithmetic support for V8HFmode if we are a power9 or later. Diff: --- gcc/config/rs6000/float16.md | 22 ++++++++++++++++++++++ gcc/config/rs6000/rs6000-c.cc | 3 +++ gcc/config/rs6000/rs6000.cc | 3 +++ 3 files changed, 28 insertions(+) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 29d970cda74f..569fe45f82a7 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -26,6 +26,10 @@ (define_mode_iterator VS_FP16 [BF HF V8BF V8HF]) (define_mode_iterator VFP16 [V8BF V8HF]) +;; Mode iterator for 16-bit floating point modes on machines with +;; hardware support both as a scalar and as a vector. +(define_mode_iterator FP16_HW [(HF "TARGET_FLOAT16_HW")]) + ;; Mode attribute giving the vector mode for a 16-bit floating point ;; scalar in both upper and lower case. (define_mode_attr FP16_VECTOR8 [(BF "V8BF") @@ -157,3 +161,21 @@ } [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")]) + +;; Convert IEEE 16-bit floating point to/from other floating point modes. + +(define_insn "extendhf<mode>2" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") + (float_extend:SFDF + (match_operand:HF 1 "vsx_register_operand" "wa")))] + "TARGET_FLOAT16_HW" + "xscvhpdp %x0,%x1" + [(set_attr "type" "fpsimple")]) + +(define_insn "trunc<mode>hf2" + [(set (match_operand:HF 0 "vsx_register_operand" "=wa") + (float_truncate:HF + (match_operand:SFDF 1 "vsx_register_operand" "wa")))] + "TARGET_FLOAT16_HW" + "xscvdphp %x0,%x1" + [(set_attr "type" "fpsimple")]) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 0af492b58218..1acafd9de46b 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -594,6 +594,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) to __bf16. */ rs6000_define_or_undefine_macro (define_p, "__bfloat16=__bf16"); rs6000_define_or_undefine_macro (define_p, "__BFLOAT16__"); + + if ((flags & OPTION_MASK_P9_VECTOR) != 0) + rs6000_define_or_undefine_macro (define_p, "__FLOAT16_HW__"); } /* Tell the user if we are targeting CELL. */ if (rs6000_cpu == PROCESSOR_CELL) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e47037ddd79d..53661e92104d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3000,6 +3000,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_mem[BFmode] = VECTOR_VSX; rs6000_vector_align[HFmode] = 16; rs6000_vector_align[BFmode] = 16; + + if (TARGET_P9_VECTOR) + rs6000_vector_unit[V8HFmode] = VECTOR_VSX; } /* DFmode, see if we want to use the VSX unit. Memory is handled