[gcc r17-2965] RISC-V: Add test cases for vwmul.vv reg overlap

https://gcc.gnu.org/g:c55a61e3cdb441909947059c5a1a4a1f8c17f34f

commit r17-2965-gc55a61e3cdb441909947059c5a1a4a1f8c17f34f
Author: Pan Li <[email protected]>
Date:   Sat Aug 1 21:04:07 2026 +0800

    RISC-V: Add test cases for vwmul.vv reg overlap
    
    Add test cases for register group overlap, please
    note it is not overlap as much as possible.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c: New test.
            * gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c: New test.
    
    Signed-off-by: Pan Li <[email protected]>
    Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>

Diff:
---
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c | 17 +++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c      | 19 +++++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c      | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c | 17 +++++++++++++++++
 .../rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c      | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c  | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c  | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c  | 17 +++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c | 19 +++++++++++++++++++
 .../riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c | 19 +++++++++++++++++++
 15 files changed, 267 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c
new file mode 100644
index 000000000000..8899d400ec66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vint16m1_t,
+  vint32m2_t,
+  __riscv_vle16_v_i16m1,
+  __riscv_vwmul_vv_i32m2,
+  __riscv_vse32_v_i32m2,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c
new file mode 100644
index 000000000000..70f25b380356
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m2,
+  vint16m2_t,
+  vint32m4_t,
+  __riscv_vle16_v_i16m2,
+  __riscv_vwmul_vv_i32m4,
+  __riscv_vse32_v_i32m4,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c
new file mode 100644
index 000000000000..2168e2f362e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m4,
+  vint16m4_t,
+  vint32m8_t,
+  __riscv_vle16_v_i16m4,
+  __riscv_vwmul_vv_i32m8,
+  __riscv_vse32_v_i32m8,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c
new file mode 100644
index 000000000000..5338a3c30f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vint16mf2_t,
+  vint32m1_t,
+  __riscv_vle16_v_i16mf2,
+  __riscv_vwmul_vv_i32m1,
+  __riscv_vse32_v_i32m1,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c
new file mode 100644
index 000000000000..e6e4e7a572db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vint16mf4_t,
+  vint32mf2_t,
+  __riscv_vle16_v_i16mf4,
+  __riscv_vwmul_vv_i32mf2,
+  __riscv_vse32_v_i32mf2,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c
new file mode 100644
index 000000000000..087cfae770a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vint32m1_t,
+  vint64m2_t,
+  __riscv_vle32_v_i32m1,
+  __riscv_vwmul_vv_i64m2,
+  __riscv_vse64_v_i64m2,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c
new file mode 100644
index 000000000000..12ad90de2a43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m2,
+  vint32m2_t,
+  vint64m4_t,
+  __riscv_vle32_v_i32m2,
+  __riscv_vwmul_vv_i64m4,
+  __riscv_vse64_v_i64m4,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c
new file mode 100644
index 000000000000..428c148141de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m4,
+  vint32m4_t,
+  vint64m8_t,
+  __riscv_vle32_v_i32m4,
+  __riscv_vwmul_vv_i64m8,
+  __riscv_vse64_v_i64m8,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c
new file mode 100644
index 000000000000..da1d3cc8095a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vint32mf2_t,
+  vint64m1_t,
+  __riscv_vle32_v_i32mf2,
+  __riscv_vwmul_vv_i64m1,
+  __riscv_vse64_v_i64m1,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c
new file mode 100644
index 000000000000..8b5fc3bde52b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vint8m1_t,
+  vint16m2_t,
+  __riscv_vle8_v_i8m1,
+  __riscv_vwmul_vv_i16m2,
+  __riscv_vse16_v_i16m2,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c
new file mode 100644
index 000000000000..afbeb4582768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m2,
+  vint8m2_t,
+  vint16m4_t,
+  __riscv_vle8_v_i8m2,
+  __riscv_vwmul_vv_i16m4,
+  __riscv_vse16_v_i16m4,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c
new file mode 100644
index 000000000000..54cc74512e0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m4,
+  vint8m4_t,
+  vint16m8_t,
+  __riscv_vle8_v_i8m4,
+  __riscv_vwmul_vv_i16m8,
+  __riscv_vse16_v_i16m8,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmul\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c
new file mode 100644
index 000000000000..6449dccf25a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf2_t,
+  vint16m1_t,
+  __riscv_vle8_v_i8mf2,
+  __riscv_vwmul_vv_i16m1,
+  __riscv_vse16_v_i16m1,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c
new file mode 100644
index 000000000000..06653d64f944
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf4_t,
+  vint16mf2_t,
+  __riscv_vle8_v_i8mf4,
+  __riscv_vwmul_vv_i16mf2,
+  __riscv_vse16_v_i16mf2,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c
new file mode 100644
index 000000000000..62b35cda0f47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vint8mf8_t,
+  vint16mf4_t,
+  __riscv_vle8_v_i8mf8,
+  __riscv_vwmul_vv_i16mf4,
+  __riscv_vse16_v_i16mf4,
+  vwmul_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmul\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */