[gcc(refs/users/meissner/heads/work255-submit)] Use vector pair load/store for memcpy with -mcpu=future
Michael Meissner via Gcc-cvs <[email protected]>
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https://gcc.gnu.org/g:a9bf98b6bd388ff941d5bf3dca3aa56418952c14 commit a9bf98b6bd388ff941d5bf3dca3aa56418952c14 Author: Michael Meissner <[email protected]> Date: Thu Aug 6 19:05:02 2026 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did not enable using the load vector pair and store vector pair instructions when optimizing memory and string built-in functions like memcpy. This patch enables using those instructions if -mcpu=future is used. This patch also documents the -mblock-ops-vector-pair option that controls whether load vector pair and store vector pairs are generated for memory and string built-in functions. 2026-08-06 Michael Meissner <[email protected]> gcc/ * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Enable using load vector pair and store vector pair instructions for memory and string built-in functions. (POWERPC_MASKS): Make -mblock-ops-vector-pair an option that is set by the -mcpu=<xxx> command line option. * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable -mblock-ops-vector-pair from influencing .machine selection. * config/rs6000/rs6000.opt (-mblock-ops-vector-pair): Document the option. * doc/invoke.texi (RS/6000 and PowerPC Options): Document the -mblock-ops-vector-pair option. gcc/testsuite/ * gcc.target/powerpc/future-3.c: New test. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 10 +++++++++- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.opt | 2 +- gcc/doc/invoke.texi | 9 +++++++++ gcc/testsuite/gcc.target/powerpc/future-3.c | 22 ++++++++++++++++++++++ 5 files changed, 42 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 365e0c6899c1..4dcdcf7c858d 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -83,9 +83,16 @@ #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ | OPTION_MASK_POWER11) -/* -mcpu=future flags. */ +/* -mcpu=future flags. + + During the development of the power10 support for GCC, using load/store + vector pair instructions for string operations was turned off by default, + because there was a use case that had really bad performance. Assume this + will be fixed in potential future machines. */ + #define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \ | OPTION_MASK_FUTURE \ + | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_DMF) /* Flags that need to be turned off if -mno-vsx. */ @@ -116,6 +123,7 @@ /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 000295340062..3d01604c7ead 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -5993,7 +5993,7 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL - | OPTION_MASK_ALTIVEC); + | OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR); if ((flags & (FUTURE_MASKS_SERVER & ~POWER11_MASKS_SERVER)) != 0) return "future"; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index d9e9de92b21a..2fbd4c308c15 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -325,7 +325,7 @@ Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags) Generate unaligned VSX load/store for inline expansion of memcpy/memmove. mblock-ops-vector-pair -Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags) +Target Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags) Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove. mblock-compare-inline-limit= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7c65c9242716..c0e643ba507e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1393,6 +1393,7 @@ See RS/6000 and PowerPC Options. -mblock-move-inline-limit=@var{num} -mblock-compare-inline-limit=@var{num} -mblock-compare-inline-loop-limit=@var{num} +-mblock-ops-vector-pair -mno-block-ops-vector-pair -mblock-ops-unaligned-vsx -mstring-compare-inline-limit=@var{num} -misel -mvsx -mvrsave -mmulhw -mdlmzb -mprototype @@ -32642,6 +32643,14 @@ constant, at most @var{num} bytes are compared before @code{memcmp} is called to compare the remainder of the block. The default value is target-specific. +@opindex mblock-ops-vector-pair +@opindex mno-block-ops-vector-pair +@item -mblock-ops-vector-pair +@itemx -mno-block-ops-vector-pair +Generate/do not generate load vector pair and store vector pair +instructions for string and memory operations. The default value is +target-specific. + @opindex mstring-compare-inline-limit @item -mstring-compare-inline-limit=@var{num} Compare at most @var{num} string bytes with inline code. diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c b/gcc/testsuite/gcc.target/powerpc/future-3.c new file mode 100644 index 000000000000..afa22228b96d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/future-3.c @@ -0,0 +1,22 @@ +/* 32-bit doesn't generate vector pair instructions. */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test to see that memcpy will use load/store vector pair with + -mcpu=future. */ + +#ifndef SIZE +#define SIZE 4 +#endif + +extern vector double to[SIZE], from[SIZE]; + +void +copy (void) +{ + __builtin_memcpy (to, from, sizeof (to)); + return; +} + +/* { dg-final { scan-assembler {\mlxvpx?\M} } } */ +/* { dg-final { scan-assembler {\mstxvpx?\M} } } */