[gcc r17-3246] RISC-V: Allow RVV register overlap for vwmacc[u].vv
Pan Li via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:2be327c50de607ab0d8c1a2295160313c7edf6db commit r17-3246-g2be327c50de607ab0d8c1a2295160313c7edf6db Author: Pan Li <[email protected]> Date: Fri Aug 7 21:10:56 2026 +0800 RISC-V: Allow RVV register overlap for vwmacc[u].vv Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the dual widen ternary vv insn vwmacc.vv and vwmaccu.vv. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 4efee02fb3b7..c2d5bf312960 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6071,23 +6071,23 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_mul_plus<su><mode>" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") - (match_operand 5 "vector_length_operand" " rvl") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (match_operand 8 "const_int_operand" " i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (any_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr")) (any_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) - (match_operand:VWEXTI 2 "register_operand" " 0")) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr"))) + (match_operand:VWEXTI 2 "register_operand" " 0, 0")) (match_dup 2)))] "TARGET_VECTOR" "vwmacc<u>.vv\t%0,%3,%4%p1"